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# Silicon (IC) Design Architect - Advanced Semiconductor Technology in Palo Alto

- **Company:** Energy Jobline
- **Location:** Albany, NY, United States
- **Experience:** Expert
- **Contract:** Permanent contract
- **Skills:** Software Debugging, Firmware, Non-Volatile Memory, High Performance Computing, Application Specific Integrated Circuits, Physical Design
- **Published:** November 14, 2026
- **Apply:** https://www.energyjobline.com/job/silicon-ic-design-architect-advanced-semiconductor-technology-palo-alto-32246436

## About the Role

* MS or PhD in Electrical Engineering, Microelectronics, or a closely related field.
 * 7+ years of semiconductor IC design experience, including technical leadership of complex mixed-signal ASIC or SoC development.
 * Demonstrated ownership of at least one mixed-signal IC or SoC from initial architecture and specification through tapeout and production.
 * Strong experience with chip-level architecture, top-level integration, floorplanning, and pad-ring design.
 * Deep understanding of analog, mixed-signal, and digital IC design methodologies and trade-offs.
 * Experience with high-voltage circuits, power management, or complex analog interfaces.
 * Knowledge of design-for-test, silicon verification, bring-up, and post-silicon debugging.
 * Experience collaborating with semiconductor packaging and physical design teams.
 * Strong technical problem-solving skills and demonstrated ability to resolve complex engineering challenges.
 * Excellent communication, cross-functional collaboration, and technical leadership capabilities.
 * Comfortable operating in a fast-paced, highly innovative startup environment., Candidates with experience in one or more of the following areas are particularly encouraged to apply:
 * Mixed-signal ASIC and SoC architecture
 * Analog front-end (AFE) design
 * High-voltage CMOS and BCD process technologies
 * Power management ICs (PMIC)
 * Memory controllers, nonvolatile memory, and integrated high-voltage drivers
 * Multi-die, chiplet, and system-in-package architectures
 * Advanced 2.5D and 3D semiconductor integration
 * Die-to-die interfaces, including UCIe
 * Custom silicon development and IP integration
 * High-performance computing and advanced semiconductor systems
 * Silicon validation, characterization, and first-silicon bring-up
 * Leading multidisciplinary silicon design teams
 * Experience developing semiconductor products in early-stage or rapidly growing technology companies

## Description

This is a senior technical leadership opportunity for an accomplished IC architect with deep expertise in analog, mixed-signal, high-voltage, power management, and digital semiconductor design.

The successful candidate will work closely with systems, circuit design, packaging, and validation engineering teams to define silicon architectures, drive chip-level integration, and deliver first-pass silicon success.

This position offers significant technical ownership, the opportunity to build and lead a silicon engineering team, and meaningful equity in an early-stage technology company.

What You'll Do

 * Lead chip-level architecture and integration for advanced mixed-signal ASICs, high-voltage drivers, analog front ends, and power management ICs.
 * Translate system-level requirements into silicon architectures, detailed block specifications, and design requirements.
 * Evaluate and select semiconductor process technologies, including standard CMOS, BCD, and high-voltage CMOS.
 * Define custom silicon versus licensed IP and commercially available component strategies.
 * Own die-level floorplanning, pad rings, bump maps, and chip-to-chip interfaces.
 * Collaborate with advanced packaging teams on multi-die integration, interconnects, and package-level design constraints.
 * Develop high-voltage isolation, ESD protection, noise partitioning, and power integrity strategies.
 * Lead top-level chip integration, including power distribution, clocking, reset, analog/digital interfaces, and timing.
 * Define design-for-test (DFT), silicon validation, and debugging strategies.
 * Drive technical design reviews, tapeout readiness, and final design sign-off.
 * Work with silicon validation, test, and firmware teams on bring-up, characterization, and troubleshooting.
 * Provide technical leadership to internal engineering teams and external semiconductor design partners.
 * Help establish scalable silicon design methodologies and engineering best practices.