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# Sr. Staff Performance Tuning Engineer (CPU PMU & Virtualization)

- **Company:** NIO
- **Location:** San Jose, CA, United States
- **Experience:** Expert
- **Salary:** $192,100.0 - $249,600.0
- **Contract:** Permanent contract
- **Skills:** ARM Architecture, C++ (Programming Language), Microarchitecture, Linux, Python (Programming Language), Kernel-Based Virtual Machine, Performance Tuning, Quick EMUlator (QEMU), Real-Time Operating Systems, Shell Script, System Software, Virtual Memory, Virtualization Technology, Xen Servers, Backend, Information Technology, Performance Monitor, Front End Software Development
- **Published:** May 22, 2026
- **Apply:** https://www.indeed.com/viewjob?jk=8d127c20d7e60fc3

## About the Role

Do you have experience in Tooling?, Do you have a Master's degree?, * Bachelor's, Master's, or Ph.D. in Computer Science, Electrical Engineering, or a related field.

 * 8+ years of experience in system performance engineering or related roles.
 * Strong understanding of computer architecture, including:
 + CPU pipelines, execution engines, and memory hierarchy
 + Interrupt architectures (e.g., GICv3/GICv4, APIC concepts)
 + MMU, virtual memory, and page table structures
 * Deep expertise with Linux performance tooling:
 + perf
 + eBPF / BCC / bpftrace
 + ftrace / trace-cmd
 * Proficiency in C/C++, Python, and shell scripting for performance tooling and automation.

Preferred Qualifications

 * Hands-on experience with ARM PMUv3 on Cortex-A55/A76/A78 or Neoverse platforms.
 * Experience with one or more virtualization stacks:
 + KVM/QEMU
 + Xen
 + seL4 or other RTOS/hypervisor environments

## Description

Performance Analysis and Optimization

 * Identify and analyze performance bottlenecks across CPU, memory hierarchy, cache, interconnect, and interrupt subsystems.
 * Leverage hardware PMU counters to measure and interpret cycles, instructions, cache misses, branch mispredictions, TLB misses, and stall cycles.
 * Compute and analyze performance metrics such as IPC, CPI, MPKI, memory bandwidth utilization, and stall breakdowns.
 * Optimize system software, applications, and drivers for throughput, latency, and performance determinism.

Virtualization Performance Tuning

 * Profile and reduce hypervisor overhead, including VM exits, interrupt injection, and stage-2 MMU translation costs.
 * Optimize vCPU placement strategies, huge page usage, and IRQ affinity for performance-sensitive workloads.
 * Analyze and tune virtio and IOMMU performance paths.
 * Investigate cross-core and cross-cluster latency issues, including IPI overhead and interrupt routing on ARM-based systems.

CPU PMU and Microarchitectural Analysis

 * Configure and interpret ARM PMUv3 and related vendor-specific performance monitoring extensions.
 * Apply Top-Down Microarchitecture Analysis (TMA) to identify frontend/backend bottlenecks.
 * Correlate PMU-derived metrics with kernel traces, source code paths, and system behavior.
 * Design and implement custom event sets tailored to workload-specific performance characterization.


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