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# Hardware Design Engineer

- **Company:** Inc. (dci)
- **Location:** Linthicum Heights, MD, United States
- **Experience:** Expert
- **Salary:** $200,000.0 - $250,000.0
- **Contract:** Permanent contract
- **Skills:** Computer-Aided Design, Computer Engineering, Digital Electronics, Field-Programmable Gate Array (FPGA), Hardware Design, OrCAD, Schematic Capture, Vivado, Scripting, Gitlab
- **Published:** June 10, 2026
- **Apply:** https://www.indeed.com/viewjob?jk=d4083deb98c52c6e

## About the Role

Do you have experience in Vendor relationship management?, Do you have a Bachelor of Science?, BS in Electrical Engineering and/or Computer Engineering

7+ years of hardware design engineering experience

 * 12+ years without a degree

EDA Expertise: Proficiency in Cadence Allegro/OrCAD

High-Speed Design: Experience with LVDS and HSS (up to 10 Gbps)

Complexity: Expert knowledge of up to 16+ layer HDI designs and IPC Class 3 standards

Full Lifecycle Ownership experience

 * From part selection/schematic capture to vendor management and test/integration

Documentation: Ability to produce high-quality technical documentation for new designs

Exposure to IA security practices, verification testing, and certification (preferred)

Familiarity with TEMPEST and RED/BLACK isolation (preferred)

FPGA design (Xilinx Vivado), Python scripting, or GitLab experience (preferred), * Hardware design engineering: 7 years (Preferred)

 * Cadence Allegro, and/or CAD: 5 years (Preferred)
 * LVDS and HSS (up to 10 Gbps): 5 years (Preferred)
 * 16+ layer HDI designs : 5 years (Preferred)
 * IPC Class 3 standards: 5 years (Preferred)

License/Certification:

 * Full-Scope Polygraph Security Clearance (Preferred)

Security clearance:

 * Top Secret (Required)

## Description

Serves as a Hardware/Printed Circuit Board (PCB) Design Engineer

Design PCBs, ensuring functionality and reliability

Deliver high quality analog/mixed signal and digital hardware designs

 * (Power, signal path, etc.)

Own the design lifecycle for security products

 * Working from initial architecture through layer HDI layout to final lab integration


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