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# Senior Principal Software Engineer - Accelerated...

- **Company:** Cadence Design Systems, Inc.
- **Location:** San Jose, CA, United States
- **Experience:** Expert
- **Salary:** $154,000.0 - $286,000.0
- **Contract:** Permanent contract
- **Skills:** C++ (Programming Language), Communications Protocols, Software Debugging, Logic Synthesis of Circuits, Emulators, Ethernet, Hardware Description Language, PCI Express, SystemVerilog, Verilog, Network Switches, State Machines, Nvme
- **Published:** June 14, 2026
- **Apply:** https://www.juju.com/job/00000000g7yv24

## About the Role

+ BS with a minimum of 10 years of experience OR MS with a minimum of 7 years of experience OR PhD with a minimum of 5 years of experience

 + Strong fundamentals in digital design, computer architecture, and system-level verification

 + Experience with hardware description languages (SystemVerilog/Verilog) and/or C/C++

 + Understanding of standard interconnect or IO protocols (e.g., PCIe, CXL, NVMe)

 + Familiarity with emulation, acceleration, or hybrid verification flows is a strong plus

 + Good debugging skills using waveforms, logs, and protocol analyzers

 + Ability to work across hardware and software boundaries

## Description

The team supports a broad portfolio of industry-standard protocols, such as PCIe, CXL, Ethernet, USB, UCIe, and emerging interconnects, and works closely with emulation platform teams, controller/PHY teams, and customers.

This role will contribute directly to the development and enhancement of PCIe/CXL AVIP and/or PCIe/CXL Virtual Bridge products, focusing on protocol functionality, performance, and robustness. Depending on the specific protocol area, the work may involve:

 + Implementing PCIe protocol features and state machines

 + Enhancing performance and scalability on emulation platforms

 + Developing debug, trace, and analysis capabilities

 + Supporting system-level and software-driven use cases via PCIe Virtual Bridge

 + Working with customers and field teams to resolve issues and deliver solutions related to PCIe and CXL

In this role, the engineer will be responsible for designing, developing, and maintaining PCIe/CXL AVIP/VB components as part of a larger protocol solution. The role is hands-on and spans feature development, validation, and customer readiness.

Key responsibilities include:

 + Designing and implementing protocol functionality in PCIe AVIP and/or Virtual Bridge components

 + Developing and debugging BFMs, transactors, and associated software interfaces

 + Ensuring correctness, performance, and scalability in emulation and acceleration flows


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