> Markdown version of [/jobs/ext/564562-senior-design-and-integration-engineer-cloud-tpu](https://www.wearedevelopers.com/jobs/ext/564562-senior-design-and-integration-engineer-cloud-tpu). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Senior Design and Integration Engineer, Cloud TPU - **Company:** Google LLC - **Location:** Sunnyvale, CA, United States - **Experience:** Expert - **Salary:** $163,000.0 - $237,000.0 - **Contract:** Permanent contract - **Skills:** Cloud Computing, Computer Networks, Computer Engineering, Microarchitecture, Software Debugging, Logic Synthesis of Circuits, Perl (Programming Language), Python (Programming Language), Performance Tuning, Scripting, Application Specific Integrated Circuits, Information Technology, Power Analysis (Cryptography), Code Inspection, Front End Software Development, Physical Design, Hardware Debugging - **Published:** June 12, 2026 - **Apply:** https://www.indeed.com/viewjob?jk=ba8185ff2a9196d3 ## About the Role Do you have experience in System performance optimization?, Do you have a Master's degree?, * Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. * 8 years of experience in RTL design. * Experience with digital design and microarchitecture design. * Cross-functional experience with DV and PD teams. * Experience in optimizing for performance, power, and area., * Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. * 10 years of RTL design experience. * 4 years of experience in power optimization and experience with power analysis tools like PowerArtist and PTPX. * Experience with Linting, CDC, RDC, LEC and experience with Scripting languages (i.e. Python or Perl). * Experience optimizing RTL solutions, RTL design methodologies and automate front-end engineering flows. * Experience in design automation, architecting RTL solutions and ASIC Synthesis flows. ## Description * Define and document the microarchitecture for digital designs within the TPU. * Partner with Verification to develop test plans and debug RTL, and collaborate with Physical Design to achieve timing, area, power, and manufacturability goals. * Drive critical power optimization and automation initiatives across all on-chip-network components and subsystems. * Support post-silicon validation and hardware debugging efforts to ensure successful deployment. * Lead the development and enhancement of internal design tools, flows, and engineering methodologies. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form. ## Related Videos - [Strange New Worlds: shaping the future of the digital age](https://www.wearedevelopers.com/videos/677-strange-new-worlds-shaping-the-future-of-the-digital-age) - [JavaScript? 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