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# AI Solution Architect II

- **Company:** HCL America Inc.
- **Location:** New York, NY, United States
- **Salary:** $290,000.0
- **Contract:** Permanent contract
- **Skills:** Capability Maturity Model Integration, Software Debugging, Electronic Design Automation, Cadence Virtuoso, Schematic Capture, Test Scripts
- **Published:** June 22, 2026
- **Apply:** https://www.indeed.com/viewjob?jk=8e5dc956f7871b69

## About the Role

Do you have experience in Technical writing within technology?, 1. Strong understanding of STD-Cell circuit design fundamentals, including CMOS logic gates and standard cell architectures.

 2. Experience with EDA tools such as Cadence Virtuoso, Spectre, and HSPICE for schematic capture, simulation, and layout editing.
 3. Good familiarity with semiconductor process technologies and design rules.
 4. Ability to prepare technical documentation and specifications for design flows.
 5. Experience in troubleshooting circuit performance issues using simulation and debug tools.
Other Requirements

 1. Optional but valuable: Cadence Certified Design Engineer (CCDE) or equivalent EDA certification.

## Description

This role focuses on supporting and enhancing standard cell circuit design activities within the semiconductor development process. The individual is responsible for maintaining, troubleshooting, and improving existing circuit features and delivering quality solutions for assigned tasks. They contribute to technical documentation and assist in gathering requirements, ensuring timely and accurate outputs in line with project objectives.
Key Responsibilities

 1. Maintain and update standard cell libraries using EDA tools such as Cadence Virtuoso, ensuring compliance with process technology specifications and resolving functionality issues.
 2. Troubleshoot and debug circuit-level challenges in STD-cell designs using simulation tools like Spectre and HSPICE, supporting enhancement and bug-fix requests.
 3. Support enhancement and minor feature development by implementing design modifications through schematic and layout editing in accordance with client or team requirements.
 4. Participate in peer code and schematic reviews, providing technical inputs based on foundational knowledge of CMOS circuit design and design-for-manufacturability.
 5. Prepare and update technical documentation, including design specifications and test reports, to facilitate CMMi compliance and meet client deliverable standards.
 6. Collaborate within the design team to collect requirements and clarify technical queries related to standard cell development and validation.


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