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# NoC Interconnect Design Engineer and Architect

- **Company:** Qualcomm
- **Location:** San Diego, CA, United States (Remote available)
- **Salary:** $115,600.0 - $173,400.0
- **Contract:** Permanent contract
- **Skills:** Microarchitecture, Software Debugging, Field-Programmable Gate Array (FPGA), Network Switches, Application Specific Integrated Circuits, Vlsi Design
- **Published:** June 21, 2026
- **Apply:** https://www.indeed.com/viewjob?jk=1b2abcb9a66e1a6b

## About the Role

Do you have experience in Tooling?, Candidates should have strong knowledge of bus protocols, synthesis tools, process nodes, VLSI design, and successful industry experience with deployment of IPs in large SoC projects while working in a collaborative environment., * Knowledge of various bus protocols (AHB, AXI, CHI, …), network on chip.

 * Strong working knowledge of architecture tradeoff analysis
 * Strong knowledge of ASIC flow (synthesis, STA, Lint), power tools
 * Skills for trouble shooting and problem solving, including RTL design, FPGA and post-silicon debug
 * Ability to define bus components micro-architecture with knowledge of performance/power/area tradeoff.
 * Ability to quickly react and adapt to changes.
 * Excellent communication skills.
 * Familiarity with CPU architecture is a big plus., * Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience., Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field.

## Description

The successful applicant will be responsible for creating micro-architecture bus components specifications as well as analyzing the performance results, deliver RTL and run tool flows. Responsibilities also include evaluating new IPs, driving new protocol deployments as well as defining system wide guidelines for IPs to inter-operate together in the SoC. Candidate should also be able to deliver RTL to the SoC team, support verification and silicon validation teams, and work with SW teams to support successful deployments of the interconnects.


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