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# Design Engineer I

- **Company:** Silicon Labs
- **Location:** Austin, TX, United States
- **Experience:** Starter
- **Salary:** $78,750.0 - $146,250.0
- **Contract:** Permanent contract
- **Skills:** Computer-Aided Design, Computer Programming, Computer Engineering, Software Debugging, Logic Synthesis of Circuits, Perl (Programming Language), Python (Programming Language), Static Timing Analysis, Tcl (Programming Language), Scripting, Physical Design
- **Published:** June 23, 2026
- **Apply:** https://www.indeed.com/viewjob?jk=0ab8d4787cbd15f8

## About the Role

Do you have experience in Semiconductor electronics?, Do you have a Master's degree?, * Master's degree in Electrical Engineering, Computer Engineering, or a related field.

 * Academic or project experience with Static Timing Analysis (STA).

 * Experience developing or working with timing constraints (SDC).

 * Understanding of digital IC design and implementation concepts.

 * Knowledge of chip-level or block-level signoff methodologies.

 * Strong analytical and problem-solving skills.

 * Effective communication skills and ability to work in a collaborative team environment.

The following qualifications will be considered a plus:

 * Experience with industry-standard STA tools such as Cadence Tempus or Synopsys PrimeTime.

 * Coursework, research, or project experience in digital implementation, physical design, or timing closure.

 * Programming or scripting experience with Python, Perl, or Tcl.

 * Familiarity with semiconductor design flows from RTL through tapeout.

 * Exposure to low-power design techniques and timing optimization methodologies.

 * Experience working with Linux/Unix environments and EDA tool flows.

## Description

You'll join the Physical Implementation Team. This team is responsible for transforming RTL designs into manufacturable silicon, driving the implementation flow from synthesis through physical design and final tapeout (GDSII). Our team works closely with Design, Verification, DFT, and Technology teams to ensure high-performance, low-power, and reliable integrated circuits are delivered on schedule. This is a great opportunity for engineers who are passionate about digital design, timing analysis, and seeing their work become real silicon.

Responsibilities

 * Support the physical implementation of digital designs from RTL through GDSII/tapeout.

 * Develop and maintain timing constraints (SDC) for block-level and chip-level designs.

 * Perform static timing analysis (STA) to identify and resolve timing violations across multiple operating conditions.

 * Assist with block-level and chip-level signoff activities, ensuring designs meet performance, power, and quality targets.

 * Collaborate with cross-functional teams including Design Engineering, Verification, DFT, and CAD to drive implementation closure.

 * Analyze timing reports and recommend design or constraint improvements.

 * Participate in debugging and resolving implementation, timing, and design integration issues.

 * Contribute to the continuous improvement of physical implementation methodologies, flows, and automation.


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