> Markdown version of [/jobs/ext/620942-data-cache-coherent-interconnect-architect-engineer](https://www.wearedevelopers.com/jobs/ext/620942-data-cache-coherent-interconnect-architect-engineer). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Data Cache & Coherent Interconnect Architect/Engineer - **Company:** Qualcomm Technologies, Inc. - **Location:** Austin, TX, United States (Remote available) - **Experience:** Experienced - **Salary:** $154,000.0 - $252,800.0 - **Contract:** Permanent contract - **Skills:** Systems Engineering, C++ (Programming Language), Computer Engineering, Microarchitecture, Software Debugging, CPU Design, Software Engineering, SystemVerilog, Verilog, Network Switches, Caching, Information Technology - **Published:** June 23, 2026 - **Apply:** https://www.dice.com/job-detail/d08fbb62-fc84-4a3c-8a3f-c9fe7e2e7d8b ## About the Role * Strong background in processor architecture and micro-architecture. * Hands-on experience with data caches and coherent interconnects. * Familiarity with cache coherence protocols (e.g., CHI, ACE, or equivalent). * Proficiency in C/C++ and/or Verilog/SystemVerilog. * Experience in IP development and performance analysis., * Prior experience with CHI protocol or similar. * Exposure to SoC integration and system-level performance modeling. * Strong analytical and debugging skills., Bachelor's degree in Electrical Engineering, Computer Science, Computer Engineering, or related field and 4+ years of Software Engineering, Electrical Engineering, Systems Engineering, or related work experience. OR Master's degree in Electrical Engineering, Computer Science, Computer Engineering, or related field and 3+ years of Software Engineering, Electrical Engineering, Systems Engineering, or related work experience. OR PhD in Electrical Engineering, Computer Science, Computer Engineering, or related field and 2+ years of Software Engineering, Electrical Engineering, Systems Engineering, or related work experience. 2+ years of experience with high-performance microprocessor design. ## Description Qualcomm, a global leader in mobile and high-performance computing, is building a new team to develop a next-generation processor. We are seeking talented engineers and architects to join a dedicated group focused on designing and implementing Data Caches and a Coherent Interconnect for cutting-edge SoCs. As a key contributor, you will be responsible for architecture definition, performance modeling, analysis, and RTL implementation of cache and interconnect subsystems. This is a unique opportunity to work on a high-impact project in a collaborative and innovative environment., * Architect and design high-performance data cache subsystems and coherent interconnects. * Develop performance models and analyze trade-offs in power, area, and latency. * Collaborate with cross-functional teams including architecture, RTL, verification, and software. * Contribute to the development of new IP blocks and integration into SoC platforms., Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). ## Related Videos - [HTTP headers that make your website go faster](https://www.wearedevelopers.com/videos/1676-http-headers-that-make-your-website-go-faster) - [More efficient software for more efficient microchips](https://www.wearedevelopers.com/videos/1164-more-efficient-software-for-more-efficient-microchips) - [Scoring 2000 Products per Request: Performance Pitfalls in Golang](https://www.wearedevelopers.com/videos/2073-scoring-2000-products-per-request-performance-pitfalls-in-golang) - [Advanced Caching Patterns used by 2000 microservices](https://www.wearedevelopers.com/videos/201-advanced-caching-patterns-used-by-2000-microservices) - [Strange New Worlds: shaping the future of the digital age](https://www.wearedevelopers.com/videos/677-strange-new-worlds-shaping-the-future-of-the-digital-age) - [Event based cache invalidation in GraphQL](https://www.wearedevelopers.com/videos/433-event-based-cache-invalidation-in-graphql) ## Related Articles - [How We Built a Worry-Free System That Runs for 10+ Years – And What We’d Do Again](https://www.wearedevelopers.com/magazine/751-how-we-built-a-worry-free-system-that-runs-for-10-years-and-what-we-d-do-again) - [Data Science & more: The Lopez dilemma](https://www.wearedevelopers.com/magazine/10-data-science-more-the-lopez-dilemma) - [Software Engineer Career: Things You Should Know](https://www.wearedevelopers.com/magazine/143-software-engineer-career-things-you-should-know) - [Dev Digest 120 - Apple and peers](https://www.wearedevelopers.com/magazine/455-dev-digest-120-apple-and-peers) - [Is Software Engineering Hard?](https://www.wearedevelopers.com/magazine/448-is-software-engineering-hard) - [Is Software Engineering Over-Saturated?](https://www.wearedevelopers.com/magazine/418-is-software-engineering-over-saturated)