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# Sr. SoC RTL Design Engineer, AI Hardware

- **Company:** Tesla Motors
- **Location:** Austin, TX, United States
- **Experience:** Expert
- **Contract:** Permanent contract
- **Skills:** Artificial Intelligence, Computer Networks, Python (Programming Language), PCI Express, Software Requirements Analysis, SystemVerilog, Tcl (Programming Language), Verilog, Scripting, Information Technology, Hardware Acceleration
- **Published:** June 24, 2026
- **Apply:** https://diversityjobs.com/career/13988830/Staff-Soc-Rtl-Design-Engineer-Self-Driving-Texas-Austin

## About the Role

* Deep knowledge of SoC architecture and AXI/CHI interconnects
 * Optimize area and power with efficient microarchitecture methods
 * Proficient in Verilog/SystemVerilog and scripting languages (e.g., Python, TCL)
 * Skilled with simulation platforms and waveformdebug tools
 * Strong grasp of logicdesign principles, timing and power implications
 * Degree in Electrical Engineering, Computer Science, or equivalent experience
 * Minimum5years of industry SoC RTL design experience
 * Experience with IEEE floatingpoint, highspeed SERDES, SMMU, GPU or PCIe is a plus

## Description

The Tesla AI Hardware team is looking for a Sr. SoC RTL Design Engineer to work on industry leading AI accelerators in Austin, TX. Candidate is expected to implement and document microarchitecture specifications, define system-level functional requirements, and deliver high quality design to achieve project targets.
What You'll Do

 * Deliver functional IP blocks into the target SoC, ensuring they meet all architectural and software requirements
 * Evaluate existing internal and external IP to understand functionality, interfaces, and integration constraints
 * Analyze and optimize timing, performance, power, and area (PPA) across the design
 * Diagnose and resolve clocktree and resetdistribution issues to guarantee robust system operation
 * Specify, microarchitect, and RTLcode accelerators, memory subsystems, and network components
 * Balance tradeoffs among functional, physical, and performance targets, making datadriven decisions
 * Partner with crossfunctional teams (implementation, verification, performance engineering) throughout the design flow
 * Design for synthesis readiness, adhering to bestpractice coding styles and tool constraints


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