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Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Front-End Design Engineer - **Company:** Qualcomm Technologies, Inc. - **Location:** San Diego, CA, United States (Remote available) - **Salary:** $115,600.0 - $173,400.0 - **Contract:** Permanent contract - **Skills:** Boolean Algebra, Perl (Programming Language), Formal Verification, Python (Programming Language), Object-Oriented Software Development, Oracle Virtual Machine, SystemC, System on a Chip, SystemVerilog, Verilog, Application Specific Integrated Circuits, Macros - **Published:** June 26, 2026 - **Apply:** https://www.dice.com/job-detail/bbf5541b-9bfe-4ce7-bf65-2f963cce4397 ## About the Role Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field. Qualifications: The ideal candidate would possess the following qualifications: * Master's degree in science, Engineering or related field * 2+ years of professional or academic experience with RTL design or verification of digital IPs * Design verification knowledge and experience with design testbench suites. * Good understanding of OOP concepts. Experience in HVL such as System Verilog, UVM/OVM & System C * Familiarity with Power-aware Verification is a plus * Good working knowledge of synthesis and STA * Knowledge of low power design techniques * Ability to work with transistor-level circuit designers * Familiarity with ASIC backend integration tools for PNR is a plus * Familiarity with IP delivery collaterals including behavior model, upf libs, LEF view, etc is a plus * Automation knowledge (python) etc. will be a significant plus Required for this role: * Education: Bachelors - Electrical Engineering, Bachelors - Science * Work Experiences: 2+ years ASIC design, verification, or related work experience * Should be able to use simulation and formal verification methodologies to execute test plans, write checkers, assertions and develop stimulus. * Strong knowledge in digital logic design (Data path and Finite Sate Machine (FSM) Design) * Skills: Verilog, System Verilog, Perl, Circuit Design ## Description In this position, you will be responsible for RTL design and verification of digital IPs used across the board in Qualcomm chips. You will have the opportunity to work on critical high-speed clock IPs, power-sequencing blocks integral to Qualcomm's low power designs, custom FIFOs and high-speed latch arrays. The position also involves close collaboration with SOC design and verification teams on specification, integration, development, and support of front-end deliverables for these Soft/Hard-Macros., Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). ## Related Videos - [Crafting Custom Frameworks with Rust: A Deep Dive into Procedural Macros](https://www.wearedevelopers.com/videos/849-crafting-custom-frameworks-with-rust-a-deep-dive-into-procedural-macros) - [Quantum DevOps - Quantum Application Development](https://www.wearedevelopers.com/videos/1441-quantum-devops-quantum-application-development) - [Modularity: Let's dig deeper](https://www.wearedevelopers.com/videos/1200-modularity-let-s-dig-deeper) - [Quantum Computing - The tiny and the big challenges](https://www.wearedevelopers.com/videos/934-quantum-computing-the-tiny-and-the-big-challenges) - [The Billion Dollar Machine: First Time Right.](https://www.wearedevelopers.com/videos/393-the-billion-dollar-machine-first-time-right) - [Reasoning about Rust: an introduction to Rustdoc's JSON format](https://www.wearedevelopers.com/videos/848-reasoning-about-rust-an-introduction-to-rustdoc-s-json-format) ## Related Articles - [Is Software Engineering Over-Saturated?](https://www.wearedevelopers.com/magazine/418-is-software-engineering-over-saturated) - [How to Write a CV and Interview if You Don't Fully Qualify For The Job](https://www.wearedevelopers.com/magazine/183-how-to-write-a-cv-and-interview-if-you-don-t-fully-qualify-for-the-job) - [Where to Find Entry-Level Software Engineering Jobs](https://www.wearedevelopers.com/magazine/397-where-to-find-entry-level-software-engineering-jobs) - [What’s the Difference between a Junior, Mid, and Senior Developer?](https://www.wearedevelopers.com/magazine/238-what-s-the-difference-between-a-junior-mid-and-senior-developer) - [Quick guide: How to write a Software Developer CV](https://www.wearedevelopers.com/magazine/37-quick-guide-how-to-write-a-software-developer-cv) - [Should senior developers refuse interview coding challenges?](https://www.wearedevelopers.com/magazine/29-should-senior-developers-refuse-interview-coding-challenges)