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# Digital Flow Enablement Solutions Architect

- **Company:** Cadence Design Systems, Inc.
- **Location:** Cary, NC, United States (Remote available)
- **Salary:** $157,500.0 - $292,500.0
- **Contract:** Permanent contract
- **Skills:** Unix, Computer Programming, Software Debugging, Logic Synthesis of Circuits, Electronic Design Automation, Perl (Programming Language), Shell Script, Static Timing Analysis, Tcl (Programming Language), Verilog, Application Specific Integrated Circuits, Epic ECSM
- **Published:** June 27, 2026
- **Apply:** https://www.juju.com/job/00000000gbgveh

## About the Role

+ Bachelor's degree with at least 12-16 years of design/EDA experience or Master's degree with at least 10 years of experience. Master's degree preferred.

 + Knowledge of standard cell and IO design, optimization and characterization methodology including LLE/LDE effects

 + Excellent digital simulation and debug skills

 + Experience with techLEF development at advanced nodes a must

 + Understanding of Liberty (.lib), Verilog & other views, such as NLDM, CCS & ECSM

 + Strong knowledge of Digital Design flows and Static Timing Analysis

 + Prior experience with ASIC digital implementation flows and EDA tools is required

 + Experience with advanced nodes (5nm and below) required.

 + Good programming knowledge in Unix, Shell scripting, perl and importantly TCL

 + Strong customer-facing communication and problem solving skills

 + Strong personal drive for continuous learning and expanding professional skill sets

 + Excellent verbal and written communication skills

Familiar with EDA tool:

 + Characterization: Liberate, Liberate MX, Liberate AMS

 + Simulators: Spectre, AMS, Xcelium

## Description

+ Leading customer engagements on standard cell library optimization and RTL->GDS enablement, including techLEF creation and updates, mapping files, and general flow development.

 + Interfacing with customers regarding digital flow enablement and methodologies, including:

 + timing characterization, including sensitivity modeling,

 + Physical view generation (LEF, GDS, abstracts, etc)

 + Logical view generation (LIB, CDL, Spectre, etc)

 + Technology LEF creation for digital tools

 + MSOA flows

 + Performing design of experiments and running Genus/Innovus to validate techLEF correctness and library performance and DRC correctness

 + Tempus timing flow development and validation

 + Working closely with R&D on tools and methodology improvements

 + Other digital P&R tasks as needed by the group

 + Processes nodes range from 1.4nm to 350nm, with majority of work at GAA advanced nodes


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