> Markdown version of [/jobs/ext/683510-principal-digital-design-engineer](https://www.wearedevelopers.com/jobs/ext/683510-principal-digital-design-engineer). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Principal Digital Design Engineer - **Company:** MaxLinear, Inc. - **Location:** Carlsbad, CA, United States - **Experience:** Expert - **Salary:** $186,000.0 - $228,000.0 - **Contract:** Permanent contract - **Skills:** Artificial Intelligence, Code Coverage, Data Link, Data Compression, Microarchitecture, Data Centers, Software Debugging, Logic Synthesis of Circuits, Microprocessors, Ethernet, Firmware, PCI Express, Systems Architecture, SystemVerilog, Systems Integration, Test Case, Verilog, IEEE 802.3, Application Specific Integrated Circuits, Power Analysis (Cryptography), Front End Software Development - **Published:** June 28, 2026 - **Apply:** https://careersus-maxlinear.icims.com/jobs/3044/senior-principal-digital-design-engineer/job?in_iframe=1 ## About the Role * Expert in digital design including micro-architecture definition and area/power/timing optimization * Solid understanding of high-speed interfaces (Ethernet/PCIe), particularly MAC/PCS (or Transaction/Data Link/PHY logical) layers, and associated clocking, reset, and CDC considerations * Experience with performance modeling and analysis, including performance constraint identification and optimization * Extensive experience with ASIC front-end design flow including RTL coding (SystemVerilog), directed/randomized verification, simulation/emulation debug, lint/CDC checks, synthesis, power analysis and timing closure support * Knowledge of communications/DSP/FEC algorithms and experience with power/area efficient fixed-point ASIC implementation a plus * Familiar with SoC integration, including clock/reset architecture, bus protocols, embedded CPUs * Strong logical and creative problem-solving skills with excellent analytical and debugging skills * Solid written and verbal communication skills * Flexibility to ramp quickly on new technologies, products, and methodologies * Self-motivated with ability to provide leadership and work effectively in fast-paced environment * BS in Electrical Engineering or related + 11 years of experience, or MS + 9 years of experience, or Ph.D. + 6 years of experience, The actual starting base salary will be determined by the match to certain role-related criteria such as educational degree(s) or equivalent, relevant work experience, skillset needed for the role, and geographic location; this is not an all-inclusive list as some roles may require unique skills or experience. ## Description MaxLinear is seeking a Senior Principal Digital Design Engineer to join our team. In this role, you will focus on the following: * Define microarchitecture for complex subsystems (e.g., 200/400G 802.3, PCIe 6/7, DSP, FEC, data compression, AI/HW accelerators) * Analyze standards (PCI-SIG, IEEE 802.3, UALink, etc) and translate into implementable RTL * Work with cross-functional project teams (DV, PD, System/Firmware) to define product specifications (PPA), system architecture, HW/SW partitioning, and execution plan * Lead improvements to design methodology to maximize efficiency and predictability * RTL implementation in SystemVerilog of communication/DSP/packet-processing functions * Block-level verification including creation of Verilog or UVM testbenches * System-level verification in UVM+SysC environments including test case creation/debug, functional coverage specification, and code coverage analysis * Perform preliminary synthesis and power estimation, including SDC constraint specification and vector-driven power analysis * Perform design quality checks including lint, CDC and DFT-readiness checks * Support emulator-based verification including debug of SW driven test cases * Post silicon bring-up support and debug in lab; support system integration and production testing * Provide technical leadership in the ASIC design team to develop and productize next generation communication and data center SoCs ## Related Videos - [The Gashlycrumb Tinies of AI Networking You Must Know (or Languish!)](https://www.wearedevelopers.com/videos/2067-the-gashlycrumb-tinies-of-ai-networking-you-must-know-or-languish) - [Playing Pong on a shoulder press machine](https://www.wearedevelopers.com/videos/100140-playing-pong-on-a-shoulder-press-machine) - [The Billion Dollar Machine: First Time Right.](https://www.wearedevelopers.com/videos/393-the-billion-dollar-machine-first-time-right) - [Building a hypercar from scratch](https://www.wearedevelopers.com/videos/607-building-a-hypercar-from-scratch) - [Docker network without Docker](https://www.wearedevelopers.com/videos/1418-docker-network-without-docker) - [Strange New Worlds: shaping the future of the digital age](https://www.wearedevelopers.com/videos/677-strange-new-worlds-shaping-the-future-of-the-digital-age) ## Related Articles - [Top-Paying Tech Jobs (with Salaries)](https://www.wearedevelopers.com/magazine/372-top-paying-tech-jobs-with-salaries) - [Highest Paying Tech Companies for Developers](https://www.wearedevelopers.com/magazine/220-highest-paying-tech-companies-for-developers) - [How Much Does a Software Engineer Make? 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