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# Embebbed software engineer

- **Company:** GMV
- **Location:** Tres Cantos, Spain (Remote available)
- **Contract:** Temporary contract
- **Skills:** Software Debugging, Digital Electronics, Field-Programmable Gate Array (FPGA), Reduced Instruction Set Computing, Static Timing Analysis, SystemVerilog, Verilog, VHSIC Hardware Description Language (VHDL), Vivado, Application Specific Integrated Circuits, Backend, Information Technology
- **Published:** May 22, 2026
- **Apply:** https://es.indeed.com/viewjob?jk=efab0e063218e513

## About the Role

Do you have experience in SoC?, For this role, we are looking for graduates in Electronic Engineering, Telecommunications, Computer Science, or similar, with a specialization in the field of digital hardware programming.

Additionally, we are seeking profiles with knowledge of digital RTL design, FPGA , SoC or MPSoC architectures, internal buses, IP integration, and functional verification; as well as previous experience in ASIC flow and handling simulation and synthesis tools.

We will also value previous knowledge of STA, DFT, scan, low-power, UPF, floorplanning or backend; verification with SystemVerilog, UVM, assertions or cocotb; embedded ARM/RISC-V processors and hardware/software partitioning; and experience with Synopsys, Cadence, Siemens EDA, Vivado, or Vitis tools.

## Description

As part of the GMV Receivers team, you will have a key role in projects related to receiver technology, contributing to the development of projects and products with strong involvement in R&D activities.

You will participate in migrating an arquitecture currently implemented on Xilinx MPSoC / FPGA to an ASIC solution. Additionally, you will have the opportunity to work on the analysis of the existing design, identification of reusable blocks, adaptation of the hardware architecture, and definition of the ASIC implementation flow.

Your main tasks would be:

 * Define and evolve the target architecture for ASIC.
 * Develop and adapt RTL blocks (VHDL/Verilog/SystemVerilog).
 * Analyze and optimize internal interfaces (buses, memories, synchronization, clocks, and resets)
 * Participate in functional verification, simulation, and design debugging.
 * Contribute to the ASIC flow: synthesis, timing analysis, CDC/RDC, DFT, and design closure.Document architecture, technical decisions, and validation results.


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