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# Senior DSP ASIC Architect - Optical Communication

- **Company:** Ciena
- **Location:** Braunschweig, Germany
- **Experience:** Expert
- **Contract:** Permanent contract
- **Skills:** Field-Programmable Gate Array (FPGA), Python (Programming Language), System on a Chip, VHSIC Hardware Description Language (VHDL), Application Specific Integrated Circuits
- **Published:** June 29, 2026
- **Apply:** https://de.indeed.com/viewjob?jk=0d552cb3b6b14099

## About the Role

Do you have experience in Python?, Do you have a Doctoral degree?, * Knowledge of ASIC and FPGA design and system-on-chip integration using VHDL and related chip design flows

 * Experience with photonic ICs and DSP co-design.



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