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# FPGA Emulation Engineer

- **Company:** QuEST Defense
- **Location:** Phoenix, AZ, United States (Remote available)
- **Experience:** Expert
- **Salary:** $150,000.0 - $180,000.0
- **Contract:** Permanent contract
- **Skills:** Board Bringup, Communications Protocols, Software Debugging, Emulators, Field-Programmable Gate Array (FPGA), Python (Programming Language), Requirements Traceability, Data Streaming, SystemVerilog, Tcl (Programming Language), Verilog, VHSIC Hardware Description Language (VHDL), Scripting, Application Specific Integrated Circuits, Hardware Testing
- **Published:** May 16, 2026
- **Apply:** https://www.indeed.com/viewjob?jk=8a0846acc0e07e7a

## About the Role

Do you have experience in System troubleshooting?, * 5+ years of experience in FPGA/ASIC verification or validation

 * Hands-on experience with hardware emulation platforms (Siemens Veloce, Cadence Palladium, Synopsys ZeBu, etc.)
 * Experience bringing up designs in emulation environments and debugging system-level issues
 * Strong understanding of RTL design and verification workflows
 * Experience bridging simulation emulation environments
 * Ability to analyze performance bottlenecks and optimize emulation runs
 * Familiarity with SystemVerilog and UVM (integration level, not pure architect focus)
 * Experience debugging interfaces, data paths, and timing-related issues
 * Ability to work across teams and drive technical solutions

Nice to Have

 * Experience with DO-254 or other safety-critical standards
 * Exposure to high-speed interfaces or communication protocols
 * Experience with scripting/automation (Python, TCL, etc.)
 * Experience supporting board bring-up or hardware validation
 * Familiarity with coverage strategies across simulation and emulation
 * Exposure to aerospace or defense programs

Tools & Technologies

 * Siemens Veloce (or equivalent emulation platform)
 * SystemVerilog / UVM (integration level)
 * Verilog / VHDL
 * Python or scripting languages
 * Simulation tools (QuestaSim, VCS, etc.)
 * DOORS/requirements traceability tools (nice to have)

## Description

* Build and maintain FPGA emulation environments using Siemens Veloce or similar platforms
 * Port and optimize RTL and test environments from simulation into emulation
 * Debug complex system-level issues that only appear at scale or in hardware-accelerated environments
 * Improve emulation performance, compile times, and runtime efficiency
 * Integrate UVM-based environments into emulation workflows (not building UVM from scratch, but making it work in emulation)
 * Support validation of high-speed interfaces and system-level data flows
 * Collaborate with RTL, verification, and systems teams to resolve design and integration issues
 * Enable full-chip and subsystem validation that cannot be achieved in simulation alone
 * Support DO-254 verification activities, including traceability and test evidence where needed
 * Help define best practices for emulation workflows across programs


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