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# Senior FPGA Engineer (VHDL/Verilog)

- **Company:** Agad Technology
- **Location:** Schelle, Belgium
- **Experience:** Expert
- **Contract:** Permanent contract
- **Skills:** Macintosh Computers, Automation of Tests, Computer Programming, Computer Networks, Software Debugging, Linux, Ethernet, Field-Programmable Gate Array (FPGA), Python (Programming Language), PCI Express, Static Timing Analysis, Tcl (Programming Language), TCP/IP, Verilog, VHSIC Hardware Description Language (VHDL), Performance Testing, ModelSim, Jenkins
- **Published:** June 19, 2026
- **Apply:** https://www.adzuna.be/details/5580512939

## About the Role

Must-have

 * Master's degree in Electronics Engineering or equivalent experience
 * Strong knowledge of VHDL and Verilog
 * Programming skills in Tcl and Python
 * Experience with timing analysis and closure
 * Experience with unit simulation testing and test automation (e.g., Jenkins)
 * Comfortable working in a Linux environment
 * Understanding of networking concepts (Ethernet, TCP/IP, MAC addressing, buffering, etc.)
 * Strong problem-solving and debugging abilities
 * Eagerness to learn and work with new, cutting-edge technologies

Nice-to-have

 * Familiarity with Xilinx FPGA tools and QuestaSim/ModelSim
 * Experience with Cocotb verification environments
 * Knowledge of high-speed interfaces (DDR4, Ethernet, PCIe, AXI4, AXI-Lite)

## Description

As a Senior FPGA Engineer, you will contribute to the development of key components within advanced networking systems, including SmartNICs and hybrid optical switches. You will be responsible for designing and optimizing VHDL and/or Verilog implementations, followed by verifying your designs through simulation using Python-based test cases and scenarios.
You will integrate your designs and IP cores into FPGA projects, perform timing analysis, and conduct on-target verification. Additionally, you will collaborate closely with software and networking teams on system-level performance testing and debugging.


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