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# Sr. Digital Design Engineer, HBM

- **Company:** Micron Technology, Inc.
- **Location:** Richardson, TX, United States
- **Experience:** Expert
- **Contract:** Permanent contract
- **Skills:** Computer Engineering, Software Debugging, Digital Electronics, Logic Synthesis of Circuits, Field-Programmable Gate Array (FPGA), Static Timing Analysis, SystemVerilog
- **Published:** May 19, 2026
- **Apply:** https://www.indeed.com/viewjob?jk=eec7f9160fbeb005

## About the Role

* Bachelor's degree or Master's degree or equivalent experience in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience.
 * Proven track record in digital circuit builds with significant work in memory or high-speed interface designs.
 * Strong expertise in SystemVerilog RTL development, HBM or DDR memory architectures, CDC strategies, low-power development, and timing-aware RTL development.
 * Knowledge of static timing analysis concepts and proven experience delivering complex builds to silicon.
 * Background working with HBM, DDR, or other high-performance memory subsystems., * Direct experience with HBM2, HBM2E, HBM3, or later architectures.
 * Experience with FPGA or emulation-based pre-silicon validation platforms.
 * Strong debugging skills across RTL, gate-level simulations, and silicon.

## Description

* Translate system-level and architectural requirements into scalable, reusable RTL builds, evaluating tradeoffs in performance, power, area, and complexity.
 * Develop high-quality SystemVerilog RTL that is synthesizable, timing-aware, power-efficient, and aligned with lint, CDC, RDC, and low-power rules.
 * Take responsibility for block-level and subsystem integration, address cross-block dependencies, and assist with synthesis, static timing analysis, and engineering change order cycles.
 * Partner with Build Verification to define verification strategies, review assertions and coverage, and analyze corner-case behaviors.
 * Debug complex functional, performance, and power issues across simulation, emulation or prototyping, and post-silicon bring-up, performing root-cause analysis and driving fixes.
 * Ensure RTL builds meet HBM protocol, timing, performance, latency, bandwidth, power, and area requirements while closing lint, CDC/RDC, and UPF checks.
 * Identify build risks early, propose mitigation approaches, and drive resolution across RTL, verification, and methodology.


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