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# Digital Design Engineer - Data Center Infrastructure Products

- **Company:** Jobot
- **Location:** Atlanta, GA, United States
- **Experience:** Expert
- **Salary:** $125,000.0 - $200,000.0
- **Contract:** Permanent contract
- **Skills:** Computer-Aided Design, Analog Electronics, Code Coverage, Computer Programming, Software Debugging, Linux, Logic Synthesis of Circuits, Perl (Programming Language), Python (Programming Language), SystemVerilog, Tcl (Programming Language), Verilog, Scripting, PIC Microcontroller, State Machines
- **Published:** June 9, 2026
- **Apply:** https://www.dice.com/job-detail/d732cf29-e847-4528-b114-fc528600003e

## About the Role

* Must have 5+ years of industry experience
 * Experience in high speed, low power digital design in advanced deep sub-micron processes
 * Proficient with SystemVeriolg/Verilog RTL, for both behavioral simulations and synthesis
 * Proficient with Design Compiler and PrimeTime
 * Programming/scripting know-how, e.g. Perl, Tcl and/or Python
 * Experience with Linux
 * Good communication skills, ability to take ownership
 * Experience with embedded micro-controllers is beneficial
 * Experience in Digital Control circuits for PMICs is beneficial
 * Experience in Clock Buffers and/or Synchronizers is beneficial

## Description

We are looking for a Senior Digital Design Engineer with 5+ years of experience who will help architect and develop RTL for various products with areas of focus in Digital Controls (e.g. PMICs), as well as Clock Buffers/Synchronizers. The ideal candidate will have RTL to GDSII flow experience using industry standard tools. In addition, knowledge of embedded micro-controllers such as RISCV and I2C/I3C/SMBus protocols are advantageous. Your contribution would be to work with other global team members in designing both building blocks for the various products, as well as designing the entire new product for the company.

Responsibilities:

 * Individual contributor to the design in a collaborative team environment
 * Design various logic & state machines in SystemVerilog/Verilog RTL
 * Develop and debug RTL, using industry-standard simulation and synthesis tools, along with LEC, CDC/RDC, Lint, DFT and STA tools
 * Provide PPA (Power, Performance, Area) and schedule estimates, as well as design specifications for the RTL
 * Coordination with Verification/AMS design teams to ensure proper operation and functional and code coverage
 * Provide floor-planning and support integration of digital & analog circuits at top level
 * Work in cooperation with the methodology and CAD teams
 * Coordination with other stakeholders in identifying needs and improvements


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