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# 30 Golden Rules of Deep Learning Performance

Stop buying more compute power to fix GPU starvation. Discover how serializing datasets, shifting augmentation, and using mixed precision can exponentially accelerate your deep learning pipelines.

- **Speakers:** Anirudh Koul
- **Event:** WeAreDevelopers LIVE
- **Published:** June 17, 2020
- **Duration:** 46:30
- **URL:** https://www.wearedevelopers.com/videos/11-30-golden-rules-of-deep-learning-performance

## Summary

Developers and data scientists often lose hours waiting for deep learning models to train, a bottleneck primarily driven by GPU starvation where expensive hardware idles waiting for the CPU to supply data. Rather than reflexively purchasing more compute power, teams can radically accelerate their pipelines by fine-tuning the underlying engine. Leveraging transfer learning and implementing straightforward code adjustments allows engineers to multiply training speeds and avoid squandering infrastructure budgets without requiring brand-new hardware arrays.

At the foundation of rapid model development is the data pipeline. Packaging datasets into serialized, 100MB chunks like TFRecords eliminates the overhead of seeking thousands of tiny files while avoiding the rigidness of single massive blocks. Implementing asynchronous prefetching creates seamless data buffers between the CPU and GPU, ensuring continuous processing utilization. Additionally, shifting intensive data augmentation tasks—such as resizing and color alteration—from the CPU to the GPU using native platform functions or packages like NVIDIA DALI drastically reduces idle computation time. Utilizing dynamic configuration parameters further abstracts the complexity of matching processing threads to available hardware cores.

Training speed can be exponentially increased by aligning mathematical operations with the physical architecture of the hardware. Utilizing mixed precision training implicitly doubles the amount of data the hardware bus can transfer by processing 16-bit floating points instead of 32-bit. Furthermore, formatting batch sizes as multiples of 8 or 128 directly activates optimal throughput on specialized hardware accelerators like Tensor Cores and TPUs. Architectural training techniques, such as progressive resizing, accelerate initial model learning by feeding lower-resolution images to capture broad shapes before introducing high-resolution details. Finally, when preparing lightweight models for edge deployment, applying 8-bit model quantization preserves 98% of predictive accuracy while shrinking the deployment footprint to a quarter of its original size.

**Keywords:** deep learning performance, gpu starvation, transfer learning, data pipeline optimization, tfrecord serialization, asynchronous prefetching, gpu data augmentation, nvidia dali, mixed precision training, hardware bus transfer, batch size multiples, tensor core throughput, cyclic learning rates, progressive resizing, 8-bit model quantization, edge device deployment

## Chapters

1. **Identifying major training inefficiencies in machine learning processes** (00:17) — Waiting for large neural networks to finish training results in wasted engineering cycles and excessive infrastructure costs.
1. **Speeding up model training cycles with transfer learning techniques** (06:56) — Reusing pre-trained convolutional neural weights directly avoids initializing large multi-layer tasks from computational scratch.
1. **Diagnosing training performance bottlenecks with visual profiling tools** (09:17) — Identifying CPU-starved graphic processors is possible using native tensorboard interfaces and terminal device queries.
1. **Optimizing custom dataset preparation to avoid file reading latency** (13:33) — Serializing custom input datasets into chunked file structures naturally prevents I/O choking while reading network files.
1. **Building asynchronous data pipelines with TensorFlow data APIs** (16:46) — Interleaving batch fetching inside background threads ensures the active GPU is constantly being fed data arrays.
1. **Offloading complex image pre-processing and augmentations to GPUs** (21:27) — Porting image manipulation procedures away from main application threads explicitly removes primary CPU processing overheads.
1. **Maximizing GPU utilization via ideal batch sizes and mixed precision** (24:14) — Adopting minimum size variables alongside properly aligned layer multiples enables aggressive tensor core processing yields.
1. **Finding the optimal learning rate automatically to simplify tuning** (29:00) — Running cyclic learning algorithms across isolated experimental trials algorithmically narrows the range of potential validation metrics.
1. **Boosting small loop logic performance by compiling execution graphs** (30:52) — Decorating standard Python callbacks internally compiles backend graphs instead of explicitly interpreting local environment sequences.
1. **Accelerating slow convergence loops using progressive image resizing techniques** (32:28) — Scaling up training complexities gradually through varying image resolutions reduces early step training spans massively.
1. **Leveraging specialized software environments optimized for local hardware specs** (34:42) — Routing default open source dependencies through optimized vendor streams yields instant processor vectorized performance benefits.
1. **Distributing local models across cloud environments and multi-GPU frameworks** (35:57) — Pushing batch workloads to cloud virtual machines drastically offsets expensive single node upfront hardware architectures.
1. **Choosing compact predefined neural network architectures for production environments** (41:32) — Committing to benchmarked open source models prevents memory overflow crashes on severely limited end user devices.
1. **Shrinking compiled models using integer quantization for inference edges** (44:21) — Downgrading compiled float networks to minimal integer values significantly shrinks deployment sizes without major capability drops.
1. **Consolidating software strategies and reviewing deep learning performance resources** (45:04) — Reviewing optimization codes provides developers a comprehensive single sheet integration pipeline for immediate model scale factors.

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- [Cost and power economics of hardware acceleration](https://www.wearedevelopers.com/videos/920-wwc24-ankit-patel-unlocking-the-future-breakthrough-application-performance-and-capabilities-with-nvidia) (from "WWC24 - Ankit Patel - Unlocking the Future Breakthrough Application Performance and Capabilities with NVIDIA")
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- [Optimizing edge model throughput to ensure real-time performance](https://www.wearedevelopers.com/videos/630-trends-challenges-and-best-practices-for-ai-at-the-edge) (from "Trends, Challenges and Best Practices for AI at the Edge")

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