Director / Principal Architect, AI Compiler & Infrastructure Optimization

AI Compiler Innovation

Lead the development and optimization of production-grade AI compilers, with a focus on technologies such as Triton, MLIR, LLVM, and XLA.

Drive research and engineering in automatic tuning engines, graph compilation, kernel compilation, operator optimization, and advanced compiler back-end technologies for AI accelerator hardware.

Software Acceleration and Performance Tuning

Analyze and resolve performance bottlenecks for multimodal models and large language models on AI accelerator platforms.

Optimize across operators, kernels, memory access patterns, memory scheduling, graph execution, and runtime performance.

Research and apply advanced techniques including automatic tuning, operator fusion, graph optimization, memory optimization, scheduling optimization, and kernel-level acceleration.

Hardware-Software Co-Design

Lead deep technical analysis of modern AI accelerator architectures, including GPUs, NPUs, TPUs, and related systems.

Identify state-of-the-art compiler, runtime, and hardware acceleration techniques, and work closely with hardware and chip design teams to improve compute efficiency, memory layout, and overall system performance.

Contribute to hardware-software co-design efforts that push the theoretical and practical limits of AI compute and memory performance.

Ecosystem and Technical Influence

Benchmark internal technologies against leading global AI infrastructure platforms and industry best practices.

Contribute to open-source compiler and infrastructure ecosystems such as Triton, LLVM, MLIR, and related projects.

Represent the team externally through technical publications, open-source contributions, industry events, academic collaborations, and technical competitions., The role offers the opportunity to build and lead a senior technical team, collaborate with leading universities and research institutions, contribute to open-source infrastructure, and influence the direction of next-generation AI compiler and accelerator technologies.

This is a senior technical leadership position for someone with strong expertise in AI compilers, accelerator architecture, performance engineering, and large-scale AI infrastructure., Technical Leadership

More than 8 years of experience in system software, AI infrastructure, compiler engineering, high-performance computing, or related areas.

Proven experience leading high-performing engineering or research teams, ideally in advanced compiler development, AI accelerator optimization, or large-scale AI infrastructure.

GPU / NPU / Accelerator Architecture

Deep understanding of GPU, NPU, TPU, or custom AI accelerator architecture.

Strong knowledge of execution units, memory hierarchy, interconnect networks, thread scheduling, data movement, memory bandwidth, latency optimization, and performance bottleneck analysis.

Compiler Expertise

Extensive practical experience in compiler front-end, middle-end, or back-end development.

Strong knowledge of compiler technologies such as Triton, MLIR, LLVM, XLA, graph compilers, kernel compilers, automatic code generation, and auto-tuning systems.

Experience optimizing compilers for AI workloads and accelerator hardware is highly preferred.

Distributed AI Infrastructure

Strong understanding of distributed training and inference at scale, particularly for large models with 100B+ parameters.

Experience with collective communication, NCCL or equivalent communication libraries, model parallelism, tensor parallelism, pipeline parallelism, memory optimization, and large-scale inference serving.

Performance Engineering

Demonstrated ability to analyze and improve end-to-end performance for large-scale AI workloads.

Experience with profiling, benchmarking, kernel optimization, operator fusion, graph-level optimization, memory scheduling, and runtime tuning.

Education

Master's or PhD in Computer Architecture, Compiler Design, High Performance Computing, Computer Science, Electrical Engineering, or a related field.

Candidates with strong records in international technical competitions, such as ACM-ICPC World Finals, IEEE/ACM system optimization competitions, or equivalent, are highly preferred.

Experience coaching or mentoring competition-level engineers or researchers is also valued.

The successful candidate will also have opportunities to participate in major industry events, technical summits, academic collaborations, and high-profile innovation projects across Europe.