Job offer

This position is part of the sovereign projects DeepGreen and CAMELIA, which are dedicated to developing hardware and software technologies for the acceleration of Artificial Intelligence workloads.

Under the DeepGreen project, work focuses on developing a complete end-to-end deployment pipeline for AI models, specifically utilizing the Aidge platform and its compilation infrastructure. This infrastructure serves as the software foundation for the developments within the CAMELIA project. As the project progresses, tasks will gradually shift toward the objectives of CAMELIA, which aims to co-develop an AI accelerator and its associated software environment. Scientific and technical challenges include, but are not limited to, compilation, execution systems, tensor arithmetic, complex system simulation, and hardware-software co-design for AI acceleration.

The primary mission is to lead the architectural design and strategic development of the compilation system. The candidate will drive the definition and standardization of high-level intermediate representations (IR) to bridge deep learning frameworks with low-level hardware, ensuring the seamless evolution of existing software infrastructures. Additionally, he will act as a high-level technical expert, managing strategic coordination with partners and providing scientific leadership to align software developments with complex hardware-driven requirements.

• Leading the architectural design and evolution of end-to-end compilation pipelines, spanning from high-level AI frameworks (such as PyTorch) to execution on specialized hardware accelerators.
• Pioneering the definition and implementation of next-generation intermediate representations (IR), advanced optimization mechanisms, and the strategic infrastructure required to integrate breakthrough features into the software platform.
• Driving research excellence in sparse computing support, tensor arithmetic, and innovative execution mechanisms for AI workloads.
• Establishing advanced analytical performance models to guide the exploration of complex hardware-software design spaces, as well as overseeing profiling, simulation, and evaluation methodologies to characterize the impact of architectural and algorithmic breakthroughs.
• Scientific leadership and supervision, including the mentorship of PhD students, postdocs, or research engineers, knowledge sharing within the consortium, and the dissemination of research results through high-impact scientific publications and strategic collaborative projects.

• Advanced Compiler Architecture: Deep mastery of compiler engineering, including graph-level optimizations, lowering techniques, and kernel generation for specialized accelerators.
• High-Level IR Design: Proven expertise in designing and standardizing advanced Intermediate Representations (IR) to bridge the gap between deep learning frameworks (e.g., PyTorch, TensorFlow) and low-level execution environments.
• Hardware-Software Co-design: Strong knowledge of hardware architectures (ASIC/FPGA), tensor arithmetic, and the development of execution models for AI acceleration.

Leadership & Professional Skills:

• Scientific Leadership: Ability to provide high-level technical direction, mentor PhD students and research engineers, and oversee complex R&D roadmaps.
• Strategic Project Management: Experience in managing technical specifications, coordinating with external industrial stakeholders, and navigating the lifecycle of sovereign research projects.
• Communication & Dissemination: Excellence in translating complex scientific concepts into actionable technical strategies and contributing to high-impact scientific publications.

Specific Requirements

Success in this role is defined by the ability to architect a transformative, end-to-end compilation ecosystem that seamlessly bridges high-level AI frameworks and next-generation hardware. The ideal candidate will move beyond simple implementation to drive the strategic vision and technical roadmap of the project, turning complex research breakthroughs into robust, industrial-grade software infrastructures. Excellence will be demonstrated through the ability to navigate the intersection of hardware and software, lead multidisciplinary teams, and act as a decisive technical authority when coordinating between academic research and industrial application.

Languages FRENCH

• Subsidized meals
• Partial reimbursement of public transport costs
• Leave: 7 weeks of annual leave + 10 extra days off due to RTT (statutory reduction in working hours) + possibility of exceptional leave (sick children, moving home, etc.)
• Possibility of teleworking (90 days / year) and flexible organization of working hours
• Social, cultural and sports events and activities
• Access to vocational training
• Social security coverage under conditions