Digital Engineer 3

PDS Inc.
Los Angeles, United States of America
yesterday

Role details

Contract type
Temporary contract
Employment type
Full-time (> 32 hours)
Working hours
Regular working hours
Languages
English
Experience level
Junior
Compensation
$ 216K

Job location

Los Angeles, United States of America

Tech stack

Agile Methodologies
Logic Synthesis of Circuits
Digital Technology
Field-Programmable Gate Array (FPGA)
Matlab
Simulink
Software Requirements Analysis
SystemVerilog
Verilog
VHDL
Application Specific Integrated Circuits
Devsecops

Job description

We are looking for you to join our team as a Principal Digital Engineer based out of Woodland Hills, CA. As a Principal Digital Engineer you will have a challenging and rewarding opportunity to be a part of our Enterprise-wide digital transformation. Through the use of Model-based Engineering, DevSecOps and Agile practices we continue to evolve how we deliver critical national defense products and capabilities for the warfighter. Our success is grounded in our ability to embrace change, move quickly and continuously drive innovation. The successful candidate will be collaborative, open, transparent, and team-oriented with a focus on team empowerment & shared responsibility, flexibility, continuous learning, and a culture of automation.

Requirements

The Digital Engineer will be responsible for design and verification of digital systems on a safety-critical development program. Candidate is required to have extensive knowledge of digital design and verification concepts. Candidate will possess strong communication skills as he or she will interface with our development program leads, senior scientists, engineering and manufacturing organizations throughout the program lifecycle. The individual will also have technical foresight to integrate the appropriate requirements, processes, procedures and tools as this development program will lead to the future generation of navigation, video & cockpit products., Bachelor's degree in a STEM field with 5 years of relevant experience; Master's degree in a STEM field with 3 years of relevant experience; PhD in a STEM field with 1 year of relevant experience

Experience with High-Speed Digital Design and Verification

Experience with FPGA/SOC/ASIC implementation (VHDL/Verilog, Synthesis, Timing Closure)

Experience with design processes including hardware requirements definition, conceptual design, detailed design, verification, production transitioning

U.S. Citizenship is required

A current/active U.S. Government Secret Clearance is required

Ability to work onsite full-time in Woodland Hills, CA, Experience with V&V technologies (System Verilog, UVM, Hardware-In-Loop)

Knowledge of Computer Architecture (Bus standards, Interrupts, Memory)

Experience with Model-based Engineering (MATLAB, Simulink, Fixed Point vs. Floating Point)

Experience with Sensors and Digital Signal Processing

Cost Account Management (CAM) certification / experience

Experience with safety critical designs (DO-254)

Communication, team building and facilitation skills

Benefits & conditions

Benefits offered to vary by the contract. Depending on your temporary assignment, benefits may include direct deposit, free career counseling services, 401(k), select paid holidays, short-term disability insurance, skills training, employee referral bonus, affordable medical coverage plan, and DailyPay (in some locations). For a full description of benefits available to you, be sure to talk with your recruiter.

About the company

To read our Candidate Privacy Information Statement, which explains how we will use your information, please visit http://www.tadpgs.com/candidate-privacy/ or https://pdsdefense.com/candidate-privacy/ The Company will consider qualified applicants with arrest and conviction records in accordance with federal, state, and local laws and/or security clearance requirements, including, as applicable: * The California Fair Chance Act * Los Angeles City Fair Chance Ordinance * Los Angeles County Fair Chance Ordinance for Employers

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