Senior Security IP Engineer

The candidate for this position will be expected and able to complete the following responsibilities:

• Own end-to-end development of security IPs from architecture and microarchitecture definition through silicon validation.

• Collaborate with architecture, SoC, firmware, verification, and physical design teams to deliver high-quality IP solutions.

• Develop high-performance, power-efficient RTL designs and drive PPA optimization across the design lifecycle.

• Lead design signoff activities including CDC, RDC, LINT, synthesis, STA, and timing closure.

• Implement and integrate hardware security technologies such as cryptographic accelerators, root-of-trust, secure boot, and key management.

• Drive pre-silicon and post-silicon debug, silicon bring-up, and root-cause analysis of complex system issues.

• Mentor engineers and champion design excellence through reviews, automation, and continuous methodology improvements.

• Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience.

Screening Requirements

• Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
• This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations.As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate's citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable, * 8+ years of hardware design experience
• Expertise in Digital Design including microarchitecture specification development and RTL coding
• Expertise in Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), and LINT closure
• Experience in developing/optimizing high speed CMOS designs and evaluating PPA tradeoffsProficiency in Verilog, System Verilog, and scripting languagessuch as Python or Perl
• Design knowledge of the industry standard bus interfaces such as AMBA AXI protocol
• Experience in basic floor planning, static timing analysis/closure and engaging with physical design teams
• Experience with driving chip design quality through design and checklist reviews
• Good communication and a self-motivated individual that can collaborate across teams within Microsoft
• Worked in leading-edge technologies: 5 nm or newer
• Experience working with Cryptography Standards e.g., AES, SHA, Elliptic Curve Cryptography is a plus.

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