Staff Hardware Design Engineer
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Job description
SiFive is seeking a Senior Hardware Design Engineer specialized in IOMMU (Input-Output Memory Management Unit) and Virtualization architectures. As RISC-V expands into data center, automotive, and high-performance computing (HPC) markets, the need for robust memory isolation and efficient virtualization is paramount.
In this role, you will lead the development of our MSI Translation Engine (MTE) . While SiFive already designed a robust IOMMU IP, we are expanding our virtualization capabilities by designing a specialized MTE that leverages IOMMU-like mechanisms specifically for Message Signaled Interrupt (MSI) translation. This component is critical for RISC-V virtualization, as it ensures that interrupts from various high-speed peripherals (PCIe, AI accelerators) are securely translated and delivered to the correct Guest OS or Hypervisor context. You will work at the intersection of core MMU design and system-level interconnects
Leveraging our unique Chisel-based hardware generation framework, you will build highly configurable IP that scales from lightweight embedded systems to complex, many-core server-class SoCs., * Micro Architecture & Design: Own the microarchitecture of the MSI Translation Engine, ensuring it meets strict latency and throughput targets for high-performance computing and automotive applications.
- RTL Implementation: Develop RTL generators using Chisel (Scala) , focusing on modularity and extreme configurability.
- Memory System Optimization: Design and optimize the MTE's internal memory hierarchy, including TLBs, MSHRs, and local metadata caches.
- Cross-Functional Collaboration: Work with Core MMU and Architecture teams to align MTE behavior with the RISC-V AIA (Advanced Interrupt Architecture) and H-extension specifications.
- Verification & Physical Design: Partner with DV teams to create rigorous test plans for complex corner cases (e.g., page faults during interrupt translation). Collaborate with Physical Design to ensure timing closure on advanced process nodes.
Requirements
- 7+ years of industry experience in RTL design, specifically focusing on memory management, interrupt controllers, or complex SoC IP.
- Deep Knowledge of Memory Systems: Proven experience with TLB design, MSHRs, cache controllers.
- Virtualization Expertise: Strong understanding of IOMMU mechanisms, two-stage address translation, and hypervisor-level memory isolation.
- Full RISC-V System with LTI (Look-aside Translation Interface): Experience with the RISC-V LTI protocol to offload address translation from the I/O device to the IOMMU/MTE, enabling efficient hardware-accelerated memory management in complex subsystems is a plus.
- PCIe Knowledge very welcomed : Familiarity with the PCIe stack, specifically regarding ATS (Address Translation Services) and PRI (Page Request Interface), and how they interact with system-level translation engines.
- Protocol Mastery: Expert-level knowledge of AMBA protocols, specifically AXI4.
- Object-Oriented Programming: Proficiency in at least one OO or functional language (Scala, C++, or Java). Experience with Chisel/Scala is highly preferred.
- Hardware Design Skills: Advanced proficiency in SystemVerilog or Verilog, with a focus on high-quality, maintainable code.
- Communication: Must be fluent in English with the ability to document complex microarchitectural specifications clearly.
- Education: MS/PhD in EE, CE, or a related technical discipline.