Staff Engineer, Design Verification Engineering
Role details
Job location
Tech stack
Job description
Define and verify interfaces, state machines, and controlling logic required to implement new products for Data Center, Energy, and Automotive applications. Develop directed and constrained random test cases in SystemVerilog. Architect, implement, and/or manage complete metric-driven SystemVerilog and UVM verification environments as determined by project complexity. SystemVerilog Assertion for Dynamic and Formal Verification. Design and maintain mixed-signal simulation (Cadence AMS); write Verilog-AMS and
Requirements
Requirements: Must have a Master's degree in Electrical Engineering, Materials Engineering, Physics, or closely related technical discipline (willing to accept foreign education equivalent) and four (4) years of experience as a Design Verification Engineer or related occupation performing module level design performing with Verilog RTL and function verification.
Alternatively, employer will accept a Bachelor's degree in Electrical Engineering, Materials Engineering, Physics, or closely related technical discipline (willing to accept foreign education equivalent) and six (6) years of experience as a Design Verification Engineer or related occupation performing module level design performing with Verilog RTL and function verification.
Must also possess the following (quantitative experience requirements not applicable to this section):
- Demonstrated Expertise ("DE") with mixed signal IC verification techniques (SystemVerilog and UVM), verification test plan creation, coverage closure, test case and regression suite development.
- DE defining, designing, and verifying experience with custom state machines and control logic for use with analog and mixed signal circuits such as data converters, linear regulators, high speed serial interfaces, and microcontrollers.
- DE defining and implementing custom digital interfaces (I2C, SPI, and UART).
- DE with logic synthesis with timing and placement constraints, timing and power analysis, logic equivalence checking, design for test, scan insertion, and ATPG.
- DE with verification tools (Xcelium or VCS), and scripting languages (Perl, Python, and C).