STA Engineer

• Support Static Timing Analysis activities for block and SoC level designs across multi-corner and multi-voltage environments.
• Develop and manage timing constraints, timing budgets, and signoff methodologies for high-performance ASIC designs.
• Own timing flow execution and drive timing convergence activities to meet overall SoC timing requirements.
• Collaborate closely with design and physical implementation teams to analyze timing requirements, debug timing failures, and improve design quality.
• Support timing closure activities including repeater planning, exception generation, ECO implementation, and analysis automation.
• Develop automation scripts and methodologies to improve timing analysis efficiency and design flow optimization.
• Work with geographically distributed teams to support project execution and timing signoff activities.

Responsibilities:

• Develop block and SoC timing constraints.
• Perform full-chip STA setup and timing signoff for multi-corner and multi-voltage designs.
• Manage timing budgeting, repeater planning, and timing exception generation.
• Collaborate with design teams to understand timing requirements and convergence challenges.
• Work with physical implementation teams to debug timing failures and improve QoR.
• Support ECO generation and timing closure activities.
• Develop scripts to automate timing analysis and design flows.
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• 10+ years of experience in ASIC implementation and CAD methodology.
• Experience closing timing for high-performance ASIC designs.
• Experience with STA constraints generation, timing analysis, timing convergence, and ECOs at block and full-chip levels.
• Experience working with multi-voltage and low-power designs.
• Experience developing automation scripts for analysis and design flow improvements.
• Hands-on experience with physical design implementation is a plus.

Skills:

• Strong expertise in Static Timing Analysis methodologies.
• Expertise with Synopsys Design Compiler and PrimeTime tools.
• Strong knowledge of multi-corner and multi-voltage timing analysis.
• Proficiency in TCL, Perl, and/or Python scripting.
• Strong analytical and problem-solving skills.
• Excellent communication and collaboration abilities.
• Ability to manage multiple projects and work with geographically distributed teams.

Should Have:

• Experience with low-power and multi-power mode design closure.
• Knowledge of ASIC physical design implementation concepts.
• Strong attention to detail and timing convergence methodologies.

Qualification And Education:

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field is preferred.