Senior Digital Design Engineer
Edison Smart®
Glasgow, United Kingdom
11 days ago
Role details
Contract type
Permanent contract Employment type
Full-time (> 32 hours) Working hours
Regular working hours Languages
English Experience level
SeniorJob location
Glasgow, United Kingdom
Tech stack
Logic Synthesis of Circuits
Field-Programmable Gate Array (FPGA)
Verilog
VHDL
Application Specific Integrated Circuits
Requirements
- Strong background in FPGA or ASIC Design
- RTL design (Verilog, VHDL)
- Understanding of testbench development
About the company
Edison Smart is working with a Semiconductor business specialising in wireless technologies.