Senior FPGA / SDR Firmware Engineer - Active Secret Clearance

Real Time Solutions, Inc.
Aberdeen Proving Ground, United States of America
yesterday

Role details

Contract type
Permanent contract
Employment type
Full-time (> 32 hours)
Working hours
Regular working hours
Languages
English
Experience level
Senior
Compensation
$ 170K

Job location

Aberdeen Proving Ground, United States of America

Tech stack

Boolean Algebra
C++
Communications Protocols
Computer Engineering
Software Debugging
Linux
Firmware
Field-Programmable Gate Array (FPGA)
Joint Test Action (IEEE Standards)
Python
Mercurial
Routing
Signal Processing
Subversion
Verilog
VHDL
Vivado
Software Repository
State Machines
GIT
SC Clearance
Software Defined Radio
Software Version Control
Hardware Debugging

Job description

Job Description: Our technology solutions firm is searching for a full-time Senior FPGA/SDR Firmware Engineer to drive the engineering lifecycle of mission-critical defense projects on-site at Aberdeen Proving Ground (APG).

Operating within a highly collaborative, rapid R&D infrastructure, you will develop, prototype, and test advanced Software Defined Radio (SDR) waveforms and signal processing pipelines directly within Field Programmable Gate Array (FPGA) logic architectures. Our group prioritizes execution, innovative thought processes, and high-impact field delivery over bureaucratic administrative processes or excessive design documentation., * Research signal processing methodologies, communication protocols, and tactical architectures.

  • Translate algorithmic models and operational parameters into working, high-performance VHDL or Verilog designs.
  • Design and deploy custom hardware blocks, logic architectures, and finite state machines (FSMs).
  • Interface with FPGA toolchains to complete timing closure, synthesis, routing, and deployment.
  • Utilize JTAG debugging methods and standard RF laboratory test equipment to validate performance on targeted hardware platforms.
  • Assist team members with integration, validation, and localized peer mentorship.

Requirements

Do you have experience in Version control?, Do you have a Bachelor of Science?, * U.S. Citizenship with an active Department of Defense (DoD) Secret Security Clearance.

  • Minimum of 3 years of engineering experience focused on Software Defined Radio (SDR) platforms.
  • Hands-on proficiency with VHDL programming for digital logic development.
  • Demonstrated experience utilizing modern FPGA tool suites (Xilinx Vivado or Intel Quartus).
  • Background navigating and developing inside a Linux OS environment.
  • Familiarity with code repositories and version control (Git, SVN, or Mercurial).

Preferred Technical Qualifications:

  • BS/MS degree in Electrical Engineering, Computer Engineering, or a highly related STEM domain.
  • Practical knowledge of RF communication principles and signal analysis.
  • Competency handling lab test equipment (Spectrum Analyzers, Vector Waveform Generators).
  • Baseline programming capabilities in C, C++, or Python for supporting scripts/applications.
  • Familiarity with hardware debugging via ChipScope, SignalTap, or JTAG interfaces.

Benefits & conditions

Pulled from the full job description

  • Tuition reimbursement
  • Health insurance
  • 401(k) matching
  • Paid time off
  • Vision insurance
  • Dental insurance
  • Paid holidays, * 4 Weeks of Paid Time Off (PTO) + 11 Paid Federal Holidays.
  • 100% Employer-paid Medical, Dental, and Vision insurance premiums for employees.
  • Fully funded HRA card ($2,000 for individual / $4,000 for family plans).
  • 401(k) Retirement Plan featuring a 4% matching contribution with immediate, 100% vesting.
  • Corporate Bonus Program (Paid annually based on milestone targets).
  • Full Tuition Reimbursement Program for ongoing professional development.

Schedule: Monday to Friday (On-site requirement at APG).

Security Clearance Statement: Candidates must possess a verifiable active security clearance to be considered for this role.

Pay: $150,000.00 - $170,000.00 per year

Apply for this position