Senior Digital Design Engineer

TRC
Johns Creek, United States of America
1 month ago

Role details

Contract type
Permanent contract
Employment type
Full-time (> 32 hours)
Working hours
Regular working hours
Languages
English
Experience level
Senior

Job location

Johns Creek, United States of America

Tech stack

Software Debugging
Logic Synthesis of Circuits
Perl
Python
Reduced Instruction Set Computing
SystemVerilog
Tcl (Programming Language)
Verilog
Scripting (Bash/Python/Go/Ruby)
State Machines

Job description

Contribute as an individual designer and technical mentor within a collaborative environment. Design and implement logic and state machines using SystemVerilog/Verilog RTL. Develop, debug, and validate RTL using industry-standard simulation, synthesis, and analysis tools (including LEC, CDC/RDC, lint, DFT, and STA). Generate PPA (power, performance, area) estimates, schedules, and detailed RTL design specifications. Collaborate with verification and AMS teams to ensure functionality, performance, and coverage goals are met. Support top-level integration, including floorplanning and digital/analog co-design. Work closely with cross-functional stakeholders to identify requirements and drive continuous improvements., Overview The Sr. Engineer, Power & Electronics will be responsible for the design and development of Chargers and peripheral equipment, as well as large Battery Energy Storage Sy…

  • 1 month ago

Requirements

They're seeking a Senior to Staff-level Digital Design Engineer (typically 4-12+ years of experience) to architect and develop RTL for a range of products. This role focuses on digital control systems (PMICs) as well as clock buffers and synchronizers. The ideal candidate will have hands-on experience with the full RTL-to-GDSII flow and a desire to provide technical leadership within a growing organization., Experience: 4-12+ years of relevant industry experience in digital design (Leveling available from Senior to Staff). Design Depth: Strong background in high-speed, low-power design using advanced deep submicron technologies. RTL: Proficiency in SystemVerilog/Verilog for both simulation and synthesis. Tools: Experience with industry tools such as Design Compiler and PrimeTime. Scripting: Experience with Perl, Tcl, and/or Python. Mindset: Strong communication skills with a proactive, ownership-driven mindset and a willingness to mentor junior talent. Preferred Qualifications Experience with embedded microcontrollers (e.g., RISC-V). Knowledge of digital control circuits for PMIC applications. Familiarity with clock buffers and synchronizers.

About the company

Scientific Games + Alpharetta, GA Scientific Games: Scientific Games is the global leader in lottery games, sports betting and technology, and the partner of choice for government lotteries. From cutting-edge bac…

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