Principal Signal Integrity & Hardware Systems Engineer (PCIe Gen

ASGN Incorporated
Santa Clara, United States of America
1 month ago

Role details

Contract type
Permanent contract
Employment type
Full-time (> 32 hours)
Working hours
Regular working hours
Languages
English
Experience level
Senior
Compensation
$ 250K

Job location

Santa Clara, United States of America

Tech stack

Data analysis
Systems Engineering
Software Debugging
Digital Electronics
Logic Synthesis of Circuits
Digital Technology
Firmware
Python
Matlab
PCI Express
Signal Integrity
Scripting (Bash/Python/Go/Ruby)
Hfss
Software Troubleshooting
Modeling and Simulation
Ansys

Job description

We are seeking an experienced Principal Signal Integrity & Hardware Systems Engineer to lead design and verification of high-performance digital hardware with a focus on PCIe Gen5/Gen6 and 25Gbps+ SerDes interfaces. The role combines advanced signal and power integrity analysis, reference board and PCB design guidance, EM/field simulation, and hands-on lab validation to ensure robust system-level performance. You will drive architecture decisions, mentor engineers, and collaborate across cross-functional teams to deliver scalable, manufacturable solutions for next-generation products., * Lead signal integrity (SI) and hardware systems engineering efforts for PCIe Gen5/Gen6 and other high-speed SerDes interfaces, driving architecture choices, budgeting, and tradeoffs.

  • Own reference board and PCB design best practices: define stackups, routing topologies, connector/cable interfaces, and layout constraints for high-speed channels.
  • Perform detailed SI and PI analysis using tools such as Cadence Sigrity, SIsoft, Ansys HFSS, and other EM solvers to model channel loss, crosstalk, reflections, and package effects.
  • Develop and run channel and link-level simulations (IBIS-AMI, eye, BER, jitter/power-aware analyses) to validate compliance with PCIe and other protocol margins.
  • Lead power integrity (PI) analysis and decoupling strategies to minimize supply noise impact on SerDes and system timing.
  • Create EM models of packages, connectors, and PCBs, and use them to inform design changes to improve signal fidelity and EMC performance.
  • Plan and execute lab validation: setup and run TDR/TDT, VNA, high-speed oscilloscope, BERT, and related measurements for debug and release verification.
  • Collaborate closely with board layout teams, package engineers, firmware, system architects, and manufacturing to resolve signal and hardware issues from pre-silicon through production.
  • Mentor and coach other engineers, establish SI/PI processes and checklists, and drive knowledge sharing across the organization.
  • Support supplier and partner engagements, including reviewing third-party PCB stackups, evaluating test fixtures, and providing technical direction for prototypes and NPI runs.

Requirements

Do you have experience in Thermal analysis?, Do you have a Master's degree?, Requirements: Signal Integrity, PCIe (Gen5/6), High-Speed SerDes, PCB Design, Power Integrity (PI) Analysis, Sigrity / Ansys HFSS, Reference Board Design, EM Modeling & Simulation, * Bachelors or Masters degree in Electrical Engineering or related field; PhD preferred but not required.

  • 5+ years of hands-on experience in signal integrity, hardware systems, and high-speed digital design with demonstrated leadership on complex products.
  • Proven experience designing and validating PCIe Gen5 and/or Gen6 links and related SerDes interfaces (protocol compliance and link margining).
  • Strong PCB and reference board design background, including stackup definition, controlled impedance routing, and connector/cable integration.
  • Proficiency with SI/PI and EM tools such as Cadence Sigrity, SiSoft, Ansys HFSS, Keysight ADS, or similar simulation suites.
  • Expertise in IBIS-AMI modeling, channel simulation, BER/eye analysis, and jitter decomposition techniques.
  • Experience with power integrity analysis and decoupling strategies for high-speed digital systems.
  • Hands-on lab experience with high-speed test equipment (oscilloscopes, VNAs, TDRs, BERTs) and troubleshooting methodologies.
  • Experience with EM/package modeling, signal/power co-simulation, and thermal/EM-aware system trade-offs.
  • Strong scripting and data-analysis skills (Python, MATLAB, or similar) to automate simulations and post-process results.
  • Excellent communication and cross-functional collaboration skills; experience mentoring engineers and defining engineering processes.
  • Ability to manage multiple projects, prioritize technical risks, and deliver to schedule in a fast-paced environment.

Benefits & conditions

Pulled from the full job description

  • Employee stock purchase plan
  • 401(k)
  • Health insurance
  • Paid time off
  • Vision insurance
  • Dental insurance
  • Life insurance, * Comprehensive medical, dental, and vision plans
  • Life insurance and disability plan options
  • 401(k)
  • RSUs
  • ESPP
  • Paid company-selected holidays & floating holidays
  • PTO - generous time off programs
  • Career growth opportunities

Apply for this position