Staff Engineer, TPU Co-Design
Role details
Job location
Tech stack
Job description
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Drive the definition and optimization of the hardware/software stack to enable performant training and serving of large ML models.
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Collaborate with research and modeling teams to innovate on model architectures, focusing on scaling, quality, and their direct impact on hardware performance.
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Lead the development of configurable architectural simulators and cycle-accurate performance models to quantify microarchitectural optimizations and evaluate architectural decisions.
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Conduct system-level performance analysis across highly distributed ML systems, innovating new methodologies to balance compute, memory bandwidth, and inter-chip network requirements.
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Engage with partners across hardware design, compiler development, and ML research to transition architectural innovations from concept to production.
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Requirements
Experience owning outcomes and decision making, solving ambiguous problems and influencing stakeholders; deep expertise in domain., + Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
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10 years of experience in computer architecture, chip architecture, or hardware-software co-design.
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Experience developing systems for performance modeling, simulation, or system analysis.
Preferred qualifications:
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Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
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Experience architecting hardware solutions or performance optimizations for large-scale ML training and inference.
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Experience with deep learning frameworks such as TensorFlow or PyTorch.
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Deep understanding of ML trends, business drivers, and the software ecosystem.
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Ability to engage and collaborate with hardware designers, software architects, and ML researchers.