SoC Architect
Role details
Job location
Tech stack
Job description
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System Design & Integration: You will be responsible for defining the high-level architecture of the SoC, determining which components will be included on the chip.
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You will collaborate with the hardware design teams to guide the implementation of the chip's physical design.
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You will coordinate with our firmware & GNSS team to ensure the SoC Architecture supports efficient execution of software, including drivers, operating systems and applications.
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You will define and implement security features to protect the SoC from vulnerabilities.
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You will keep up with the advances in the semiconductor industry and make sure the SoC architecture remains scalable and adaptable for future generations of products.
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Managing product timelines and deliverables, making sure that the SoC Development follows the planned schedule and stays within budget., At Qualinx, we believe that great work starts with a great environment, pioneering technology and a fun dynamic market to address. Here s what you can expect when you join our team:
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Ownership and Impact: We offer employee equity, giving you the opportunity to share in the success you help create.
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Well-being Matters: Your physical and mental health are important to us. We provide access to wellness resources, including company discounts and a free mental healthcare platform.
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Global Talent, Local Support: If you're relocating from abroad, we provide full support throughout the visa process to ensure a smooth transition.
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Future-Focused Benefits: We contribute to your pension savings to help you plan ahead with confidence.
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Inspiring Workspace: Work from a modern and vibrant, well-equipped office designed to help you do your best work.
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Scale-up Team Spirit: We celebrate our wins together with fun quarterly events think great food, games, and unforgettable experiences.
Requirements
Qualinx is looking for a result-driven and conscientious senior SoC Architect. Someone who thrives in an environment where your proactive and can-do attitude is highly appreciated. The ideal candidate for this role must have:
- Minimum of 12 years experience in RTL Design, RTL Verification, CPU-based Chip/Components Concepts and Architecture.
- Deep understanding of ARM MCUs Subsystems, Memory Controllers, and memory architectures (e.g., SRAM, ROM, Flash, NVMe ).
- At least 10 years experience with the Digital ASIC Flows, RTL design, Design Verification, Debug and Trace methodologies, Test (e.g., DFT, JTAG, Scan, BIST).
- Solid understanding of chip packaging.
- Proficient in hardware-software interface design, including device drivers, firmware, and low-level software optimizations.
- Strong problem-solving skills to troubleshoot and resolve architectural issues related to SoC integration, performance, and power efficiency.
- Experienced with silicon bring-up, validation, and post-silicon debug methodologies.
- Practical experience with IP integration, including integration flows, interconnect design (e.g., AMBA, AXI, AHB), and managing key IP integration architecture tasks.
- Deep understanding of peripherals, Pin Function Assignment, and multiplexing, as well as familiarity with various communication protocols (e.g. MIPI, LVDS, SPI, I2C, UART).
- Experience in analog-digital interface design, including RF and Analog components like PLL, ADC, DAC, LNA, PA, DCDC, LDO integration, and layout constraints for minimizing noise and signal interference.
- Knowledge of low-power design techniques, including clock gating, power gating, and multi-voltage domains (UPF/CPF).
- Deep understanding of library selection and design, with a focus on leakage power-aware methodologies to optimize performance and power trade-offs.
- Hands-on experience with IP selection to meet the specific needs of the design.
- Strong experience in selecting appropriate I/O technologies and designing for signal integrity, noise resilience, and power efficiency.
- Strong knowledge of pad ring placement and ESD strategy.
- In-depth expertise in clock and reset architecture design, including low-jitter clock distribution networks, clock domain crossing issues, and reset synchronization.
- Solid understanding of power management units and implementing various power sequencing schemes, including wake, sleep, and deep sleep modes for power efficiency.
- Solid Knowledge in signal processing, communication system.
- Exposure to all aspects of RFIC system design.