Design Verification Engineer (Silicon Engineering)
Role details
Job location
Tech stack
Job description
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Responsible for digital ASIC verification at block and system level
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Write and review test plans, develop test harnesses and test sequences
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Develop SystemVerilog testbench infrastructure (both UVM and non-UVM) for testing designs, including DSP blocks
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Responsible for test plan execution, running regressions, code and functional coverage closure
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Automate test case generation by using Python and MATLAB programs
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Contribute towards pre-silicon verification, chip bring-up and post-silicon validation
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Be a hands-on self-starter who can execute the steps required to fully verify a complex digital designs
Requirements
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Bachelor's degree in electrical engineering, computer science or computer engineering
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1+ years of experience with design verification and test bench development
PREFERRED SKILLS AND EXPERIENCE:
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Advanced degree in electrical engineering or computer engineering
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Experience with verification methodologies such as UVM
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Strong object-oriented programming knowledge
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Strong problem-solving and coding skills
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Experience in constrained random verification
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Expertise in developing test plans, implementing coverage models, and analyzing results
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Experience with scripting languages, e.g. Python for automation
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RTL design, chip bring-up, and post-silicon validation experience
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Ability to work in a dynamic environment with changing needs and requirements
ADDITIONAL REQUIREMENTS:
- Ability to work extended hours and weekends as needed to meet critical milestones, + To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here (https://www.pmddtc.state.gov/?id=ddtc_kb_article_page&sys_id=24d528fddbfc930044f9ff621f961987) .