Senior DRAM Security Test Engineer

The Senior DRAM Security Test Engineer develops advanced security validation infrastructure used to assess the resilience, robustness, and effectiveness of security mitigations in modern memory products. This role combines FPGA development, software engineering, AI-assisted development, automation, and memory architecture expertise to create scalable platforms capable of accomplishing complex DRAM validation and characterization workloads., * Design, develop, and maintain advanced security-focused DRAM test infrastructure employed to verify memory resilience, mitigation effectiveness, and security-relevant behaviors.

• Develop FPGA-based platforms capable of accomplishing complex DRAM command sequences with nanosecond-level timing precision and high-throughput operation.
• Build software frameworks, automation systems, and execution pipelines that translate high-level security test objectives into hardware-executable workloads.
• Use AI-assisted development tools such as Claude and other LLMs to speed up software development, RTL generation, debugging, automation, test creation, and technical documentation.
• Develop tools and workflows that support quick prototyping, characterization, and deployment of new security validation methodologies.
• Create security-focused test capabilities used to evaluate memory disturbance mechanisms, attack surfaces, mitigation behavior, fault conditions, and adversarial access patterns.
• Integrate host software, FPGA platforms, PCIe interfaces, and DRAM subsystems into scalable validation environments supporting large characterization and analytics campaigns.
• Partner with Product Security researchers, DRAM architects, and development teams to develop threat-informed validation strategies and boost security testing effectiveness.
• Analyze results from large-scale validation campaigns and develop automated workflows that improve triage, insight generation, root-cause analysis, and reporting.
• Drive continuous improvements in platform scalability, maintainability, developer productivity, and test execution efficiency through automation and AI-enabled engineering practices.
• Document architecture, workflows, development standards, and validation methodologies while providing technical leadership and mentorship across engineering teams.
• Define and complete the roadmap for next-generation DRAM security test infrastructure, enabling faster evaluation of emerging threats, mitigations, and architectural enhancements.

• BS in Electrical Engineering, Computer Engineering, or a related field, or equivalent experience.
• Proven experience with FPGA build using Verilog, SystemVerilog, or VHDL.
• Skilled in FPGA development environments including Xilinx Vivado or Intel Quartus.
• Strong software development skills in Python and/or C++.
• Experience with hardware/software integration and automation.
• Understanding of digital build, memory systems, and test methodologies.
• Excellent debugging, problem-solving, and documentation skills.
• Experience working with Claude or comparable AI-supported software development tools to speed up coding, debugging, automation, test generation, and documentation., * Experience with DRAM architecture, memory subsystems, or JEDEC protocols.
• Familiarity with ATE, FPGA-based validation systems, or custom test platforms.
• Established experience in building automated characterization and validation workflows.
• Knowledge of PCIe, AXI, DMA, and high-performance data movement architectures.
• Experience in improving test coverage, throughput, and validation efficiency through custom tooling and automation.

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