Senior FPGA Engineer

We are seeking a Senior FPGA Engineer to lead the architecture, design, verification, and debug of high-performance FPGA-based systems. The role requires hands-on implementation experience with FPGA development flows and HDL languages (Verilog and VHDL) to deliver robust RTL, meet timing and power targets, and support system-level integration. The Senior FPGA Engineer will work cross-functionally with hardware, firmware, and system teams to deliver production-ready FPGA solutions for high-speed, mission-critical applications., * Lead RTL design and implementation using Verilog and VHDL for complex FPGA-based systems.

• Develop and maintain reusable IP cores and design libraries, ensuring code quality and adherence to coding standards.
• Perform functional verification and simulation of designs, create testbenches, and work with verification tools to ensure correctness.
• Optimize designs for timing, resource utilization, and power; perform timing closure using industry EDA tools.
• Integrate and validate high-speed interfaces (e.g., PCIe, SERDES, Ethernet) and support signal integrity and board-level bring-up.
• Debug and triage hardware issues using oscilloscopes, logic analyzers, and internal FPGA debug (e.g., ILA/SignalTap).
• Work with synthesis, place-and-route, and bitstream generation flows in tools such as Vivado and Quartus; coordinate with EDA tool vendors as needed.
• Collaborate with system architects and PCB designers to define interfaces, constraints, and test plans.
• Mentor junior engineers, lead design reviews, and contribute to design documentation and release artifacts.
• Support manufacturing handoff, field diagnostics, and post-silicon validation activities.

• Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or related field.
• 5+ years of professional experience in FPGA design and development with demonstrated ownership of complete design cycles.
• Strong proficiency in Verilog and VHDL (required).
• Proven experience with FPGA platforms and tool flows (Xilinx/AMD Vivado and/or Intel/Altera Quartus).
• Experience with RTL design, synthesis, timing constraints (SDC), and timing closure methodologies.
• Experience with SystemVerilog, UVM, or advanced verification methodologies is a plus.
• Hands-on experience with high-speed digital design, SERDES, and interface protocols (PCIe, Ethernet) is desirable.
• Proficiency in hardware debug tools such as oscilloscopes and logic analyzers; familiarity with internal FPGA debug cores (ILA, SignalTap).
• Familiarity with logic EDA flows, IP integration, and vendor IP (Xilinx/Altera/Siemens) is advantageous.
• Strong problem-solving skills, excellent communication, and ability to work independently and within cross-functional teams.

Pulled from the full job description

• Health insurance
• 401(k) matching
• Paid time off
• Vision insurance
• Dental insurance
• RSU, * Medical
• Dental
• Vision
• PTO
• 401k w/ match
• Potential for RSUs

We are a communications software/hardware company that has proudly been in business for over 20 years! We are on a mission to provide the highest quality service possible and bridging the digital divide across the globe. We work across a variety of different industries and one of the first global leaders in our space that is constantly innovating and working with the latest technologies.