FPGA Engineer

Our client is expanding their hardware engineering organization and is looking for a Mid / Senior FPGA Engineer to support advanced RISC V based processor development. In this role, you will integrate RTL releases into FPGA based emulation and prototyping platforms. You will enable validation and demonstration of complex processor IP, working on large FPGA devices and optimizing resource usage, timing and performance. The role requires close collaboration with software, firmware and hardware teams to deliver reliable emulation systems used across development and client demonstration environments. Location: Barcelona, Spain - Hybrid

Responsibilities: As a FPGA Engineer, Mid / Senior, your broad responsibilities will include but are not limited to:

• Integrate RTL code releases into new FPGA designs
• Configure FPGA peripherals to maximize performance of RISC V prototyping platforms
• Implement RTL modules to provide optimal IO configurations for the core under emulation
• Apply timing and placement constraints to achieve target performance margins
• Optimize device resource usage across large FPGA architectures
• Interact with software and firmware teams to understand feature requirements
• Maintain and improve internal FPGA platforms and resource pools
• Support development of demonstration systems used with clients
• Contribute to debugging and validation activities

Mid FPGA Engineer

• 4 to 7 years of relevant FPGA experience

• Experience with Xilinx or Altera FPGAs

• Hands on experience with Vivado or Quartus

• Knowledge of Verilog, SystemVerilog or VHDL

• Experience with FPGA timing and placement constraints

• Knowledge of AXI4, AXI4 Lite, UART, I2C or SPI is valuable

• Experience with Tcl or Bash scripting

• Comfortable working in Linux based environments

• English level C1 Senior FPGA Engineer

• 7 plus years of industrial experience

• Strong experience using FPGA Integrated Logic Analyzer tools

• Strong knowledge of AXI4, AXI4 Lite, UART, I2C and SPI protocols

• Experience with SDC syntax for timing and placement constraints

• Experience with Git version control

• Knowledge of C, C++ or Python

• Ability to work independently across emulation, prototyping and validation flows Preferred / Valued knowledge: *Experience working with RISC V architecture is highly valued, especially within processor, SoC, RTL, verification, firmware, software, PCIe, DDR, PCS, DFT, Physical Design or hardware environments.

• Flexible working hours (office open between 7 AM and 9 PM, employees manage their own schedule)

• Hybrid working model

• One week per year work from anywhere

• 25 days annual leave plus December 24 and 31

• €150 per month food allowance ( €1800 per year additional compensation)

• Private medical insurance

• One time relocation bonus paid with the first salary

• Support with housing search through an agency

• Visa support if required

• Relocation support for family

• Virtual shares

• Language classes (Spanish, English, Catalan)

• Tax incentive Inscribirse en esta oferta Recibir ofertas similares por correo electrónico Al crear una alerta, aceptas nuestros Términos y condiciones y Política de privacidad, y el uso de cookies.

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