Senior / Staff Digital Design Engineer

As a Senior / Staff Digital Design Engineer, you will drive the digital core development from RTL to final GDS, ensuring high-quality, low-power designs. You will work with verification engineers to identify and resolve issues early, contribute to block-level architecture, and support the evolution of digital IP for current and upcoming platforms., * Lead digital core design for sophisticated power management solutions.

• Develop new IP and optimise existing designs, defining effective block-level architectures.
• Collaborate with verification teams to ensure functionality and performance before tape-out and for subsequent revisions.
• Manage synthesis, timing closure, DFT, and coordinate physical implementation with external design partners.
• Document design work and maintain clear internal technical specifications.
• Apply low-power design techniques, including clock gating, while producing robust RTL code.

• Degree in Electrical / Electronic Engineering (MEng preferred) or equivalent
• Strong experience in SystemVerilog RTL design and verification across the full design and synthesis flow.
• Familiarity with synchronous and asynchronous design, and low-power techniques.
• Proficiency with Cadence or equivalent design and simulation tools; scripting experience (Python, TCL, CSH) highly desirable.

• Base salary range: £65,000-£75,000 per year, depending on experience.
• Additional benefits include performance bonuses, equity opportunities, and standard industry benefits.

A leading Semiconductor company is looking for an experienced Senior / Staff Digital Design Engineer to lead digital design initiatives for advanced power management ICs. This role provides ownership of both existing IP and new designs, with close collaboration across multidisciplinary teams.