WeAreIn for jobs that impact everyone’s life.Build the future nobody’s dreamed of yet… are you ready to rethink the impossible?As a Principal Engineer DSP PHY Digital Design in our Research & Development team, you’ll have the opportunity to merge creativity with your technical expertise by shaping the future of technology, driving groundbreaking projects, and bringing new ideas to life.Are you in?, * Architect and simulate DSP signal chains for automotive Ethernet PHYs: define features, performance targets, and algorithm specs for mixed-signal and digital teams

• RTL Design and Verification
• Develop equalization and adaptation algorithms for wireline channels(e.g., FFE/DFE, adaptive filtering), including fixed-point considerations
• Design and implement timing recovery/synchronization blocks (CDR, tracking loops), including jitter tolerance and stability/latency tradeoffs
• Contribute to detection and coding / FEC integration: soft-information interfaces, performance/complexity tradeoffs, and linkKPIs
• Build bit-true / fixed-point models and reference implementations primarily in C++ and MATLAB (Python optional, not core
• Define verification metrics and stress tests (BER/FER, convergence time, corner cases) and partner with DV to ensure coverage
• Support silicon bring-up and lab debug: correlate model silicon, root-cause issues, and iterate on algorithms/specs
• Collaborate across architecture, design, verification, and applications to deliver implementable and testable solutions

• B.S. + 10 years (or M.S. + 7 years) in Electrical Engineering, Computer Engineering, or related field
• Strong fundamentals in digital communications and DSP, including probability/statistics
• Practical experience in high-speed wireline DSP, including some mix of: FFE/DFE, adaptation, CDR, MLSD/Viterbi concepts, FEC integration, fixed-point modeling
• Strong C++ and MATLAB skills for algorithm development, modeling, and analysis

Preferred qualifications

• Experience with automotive Ethernet PHY/SerDes constraints(robustness, low latency, interoperability, EMI resilience)
• Familiarity with ADC-based receiver architectures and calibration concepts
• Experience translating algorithms into RTL-friendly specs(throughput/latency budgeting, memory/compute sizing, state-machine behavior)
• Knowledge of link startup/training / autoneg concepts and system validation
• Exposure to standards work (e.g., IEEE 802.3) or cross-company technical leadership

As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener., Employment at Infineon is contingent upon proof of your legal right to work in the United States under applicable law, verification of satisfactory references and successful completion of a background check and drug test, and signing all your on-boarding documents.

In some instances, if applicable, U.S. export control laws require that Infineon obtain a U.S. government export license prior to releasing technologies to certain persons. This offer is contingent upon Infineon’s ability to satisfy these export control laws as related to your employment and anticipated job activities. The decision whether or not to submit and/or pursue an export license to satisfy this contingency, if applicable, shall be at Infineon’s sole discretion. Infineon Technologies takes data privacy and identity theft very seriously. As such, we do not request personally-identifiable information (PII) from applicants over the internet or electronically. Please kindly refrain from disclosing your PII electronically during the application process or to unauthorized websites that may purport to be Infineon or any of our affiliates.