FPGA Architect
Q Tech
Barcelona, Spain
26 days ago
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Role details
Contract type
Permanent contract
Employment type
Full-time (> 32 hours)
Experience required
7 years minimum
Working hours
Regular working hours
Job source
Tech stack
C++ (Programming Language)
Digital Electronics
Field-Programmable Gate Array (FPGA)
Static Timing Analysis
SystemVerilog
Job description
They’re looking for someone with strong architectural thinking who still enjoys being hands-on.
- Define FPGA architecture aligned with the overall system
- Decide what belongs in hardware vs software
- Design synchronization and communication layers across FPGAs
- Collaborate closely with software teams (C++) and technical stakeholders
- Translate complex use cases into real solutions
- Stay involved in implementation (~50% hands-on)
The team
- Barcelona-based R&D team, highly international (40+ nationalities)
- Close collaboration with US-based teams
- Working alongside another very senior FPGA engineer
- Strong engineering culture, focused on quality and long-term thinking (not delivery-driven)
- SystemVerilog (core)
- FPGA validation, simulation, static timing analysis
- C++ environment (understanding HW/SW interaction is key)
Requirements
- 7+ years of experience in digital electronics / FPGA
- Proven experience as an FPGA Architect
- Solid background in validation, simulation, and timing
- Collaborative, with strong technical judgment
Why this could be interesting
- Highly complex product with real impact in cutting-edge industries
- Deep technical challenges (not maintenance or trivial legacy work)
- Growth phase with strong product expansion
Benefits & conditions
You would be working on a product that enables multiple instruments (each with its own FPGA) to behave as a single, tightly synchronized system in real time.
- Distributed systems with multiple FPGAs
- Deterministic execution with phase coherence
- Synchronization and communication across thousands of channels
- Use cases in quantum computing, radar, 5G/6G, and MIMO systems
This is not an isolated IP problem - it’s a system-level architecture challenge.
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