Senior Verification Engineer - Core Testbench & Dv Methodology Lead

Job Description Our partner is expanding their hardware verification team and is looking for a Senior Verification Engineer to own core testbench development and verification methodology for advanced high performance processor development.In this role, you will own and evolve the top level core verification environment, working closely with design verification, RTL, architecture, software and infrastructure teams.You will play a key role in ensuring verification quality by improving the core UVM testbench, integrating unit level verification IP, driving coverage closure, identifying cross block verification gaps and improving methodology, tooling and CI flows.Location : Barcelona, Spain - Hybrid Responsibilities: As a Senior Verification Engineer, your broad responsibilities will include but are not limited to: * Own and evolve the top level core testbench and UVM environment * Integrate unit level verification IP into the core testbench * Reuse block level checkers, monitors and coverage at top level * Extend and improve test suites * Own functional and code coverage at core level * Review regression and coverage results * Drive coverage closure across units * Identify verification gaps between blocks and units * Review assume and guarantee relationships across testbenches * Own compile, regression, coverage and CI flows * Keep verification regressions stable and efficient * Improve scripts, tools and verification flows * Work with EDA vendors on tool capability improvements * Review block and core level testbench architecture * Mentor engineers on coverage driven and assertion based verification Requirements: * 10 plus years of design verification experience * Strong processor core or complex microarchitecture verification experience * Strong SystemVerilog and UVM * Experience building reusable multi agent environments * Strong functional coverage and verification planning experience * Strong Questa experience * Visualizer, Verdi, VCS or Xcelium experience * Strong Python scripting * Bash or Tcl scripting * CI, regression and verification infrastructure experience * SVA and assertion based verification experience * Understanding of cross block verification contracts * Bachelor or Master in a relevant technical field * English level C1 Preferred / Valued knowledge: * RISC V core verification experience is highly valued * Formal verification experience is valued * Emulation experience with Veloce or ZeBu is valued * AXI, CHI or bus interface knowledge is valued * CPU, GPU, NPU, AI accelerator or high performance SoC experience is valued What’s in it for you?Our client offers an exciting, challenging role in a collaborative, dynamic environment.The right person will find many career growth opportunities in their company, whether you want to advance your technical skills or aspire to leadership in the future.Benefits: Flexible working hours (office open between 7 AM and 9 PM, employees manage their own schedule) Hybrid working model One week per year work from anywhere 25 days annual leave plus December 24 and 31 €150 per month food allowance Private medical insurance One time relocation bonus paid with the first salary Support with housing search through an agency Visa support if required Relocation support for family Virtual shares Language classes (Spanish, English, Catalan) Tax incentive

Location : Barcelona, Spain - Hybrid Responsibilities: As a Senior Verification Engineer, your broad responsibilities will include but are not limited to: * Own and evolve the top level core testbench and UVM environment * Integrate unit level verification IP into the core testbench * Reuse block level checkers, monitors and coverage at top level * Extend and improve test suites * Own functional and code coverage at core level * Review regression and coverage results * Drive coverage closure across units * Identify verification gaps between blocks and units * Review assume and guarantee relationships across testbenches * Own compile, regression, coverage and CI flows * Keep verification regressions stable and efficient * Improve scripts, tools and verification flows * Work with EDA vendors on tool capability improvements * Review block and core level testbench architecture * Mentor engineers on coverage driven and assertion based verification Requirements: * 10 plus years of design verification experience * Strong processor core or complex microarchitecture verification experience * Strong SystemVerilog and UVM * Experience building reusable multi agent environments * Strong functional coverage and verification planning experience * Strong Questa experience * Visualizer, Verdi, VCS or Xcelium experience * Strong Python scripting * Bash or Tcl scripting * CI, regression and verification infrastructure experience * SVA and assertion based verification experience * Understanding of cross block verification contracts * Bachelor or Master in a relevant technical field * English level C1 Preferred / Valued knowledge: * RISC V core verification experience is highly valued * Formal verification experience is valued * Emulation experience with Veloce or ZeBu is valued * AXI, CHI or bus interface knowledge is valued * CPU, GPU, NPU, AI accelerator or high performance SoC experience is valued What’s in it for you?

Our client offers an exciting, challenging role in a collaborative, dynamic environment. The right person will find many career growth opportunities in their company, whether you want to advance your technical skills or aspire to leadership in the future. Benefits: Flexible working hours (office open between 7 AM and 9 PM, employees manage their own schedule) Hybrid working model One week per year work from anywhere 25 days annual leave plus December 24 and 31 €150 per month food allowance Private medical insurance One time relocation bonus paid with the first salary Support with housing search through an agency Visa support if required Relocation support for family Virtual shares Language classes (Spanish, English, Catalan) Tax incentive