Hardware Engineer, RTL/PD

As an RTL and PD Design Engineer at Normal, you will take and optimize RTL through synthesis and the backend to produce GDSII ready for tapeout. This work sits at the intersection of classical ASIC design, novel computing architectures, and a development environment where the hardware and the algorithms are built together, not in sequence

You will own RTL from microarchitecture to tapeout: writing microarchitecture specifications, creating synthesizable SystemVerilog, working with design verification engineers to fully test the design using conventional and formal methods. You will also take the synthesized design through the backend, including detailed place and route, CTS, timing closure, LVS/DRC, ultimately delivering fab-ready GDSII. Because Normal’s chips are not standard accelerators, the RTL engineer here is closer to first-principles decisions than at a larger company. You will be shaping architecture and novel chip design, not just implementing it.

This is a role for an engineer who collaborates effectively across teams, including architecture, verification, RTL design, and physical design. The strongest candidates have written RTL, and taped out silicon that means the design and physical constraints, and are comfortable working in an environment where the specification is still being developed in parallel., * RTL Design: Write and own synthesizable RTL in SystemVerilog across blocks ranging from datapath logic to control and memory interfaces.

• Microarchitecture: Work with architecture to translate high-level specifications into implementable microarchitectures.
• Verification: Work closely with the verification team to review verification plans, assist on debug, and become a partner in closing coverage.
• Physical Design:Take synthesized RTL gates through the full backend design flow, including floorplanning, detailed place and route, CTS, DFT insertion, timing closure, and LVS/DRC.
• Design Reviews: Participate in design reviews and contribute to architecture decisions, not just implementation.
• Tapeout & Bring-up: Create and signoff tapeout checklists, and support post-silicon characterization bring-up as needed.

• Hands-on experience writing production RTL in SystemVerilog and closing it through synthesis and place-and-route
• At least three tapeouts in your background, from any node and any company size
• Experience working on datapaths, pipelines, or custom logic where the microarchitecture was not fully specified upfront
• Strong debugging instincts across simulation, waveforms, and formal counterexamples
• Ability to work directly with architects, design verification, and fab representatives

Bonus Points

• Experience at an AI chip company where design, verification, and PD were tightly coupled
• Familiarity with RISC-V or other open ISAs
• Experience with AI-assisted RTL or EDA tooling in your design workflow

Normal Computing builds silicon that turns thermal noise from an obstacle into a computational resource. Conventional chips spend most of their energy forcing determinism onto physics; ours compute with it. Stochastic, in-memory, asynchronous: the result is 10-100× more AI inference per dollar, per watt.

We co-design the full stack: AI-native EDA systems in production with the world’s largest semiconductor companies, and the advanced ASICs they make possible. Backed by $85M+ from the world’s leading deep-tech investors and built by scientists, engineers, and operators from the labs that built modern computing.

Normal works as one team across New York, Silicon Valley, London, Copenhagen, and Seoul. We hire people who want the hardest version of their craft, across every discipline, at every seniority.