RTL Design Engineer

Experteer Overview In this role you will contribute to designing and implementing RTL for Mythic’s next-generation AI processor, enabling high-performance, low-power hardware. You will work within a cross-functional team to translate a custom dataflow architecture into silicon, tackling timing, power, and area challenges. You’ll collaborate with architects, verification, and physical design to ensure coherent integration and functional correctness. This is a hands-on role in a cutting-edge analog-digital AI hardware space, offering impact across edge and data-center applications with a strong emphasis on practical design excellence. Compensation / Benefits * Design and implement RTL for Mythic’s next-generation AI processor * Develop and optimize high-performance, low-power datapaths, controllers, memory subsystems and interconnects * Collaborate with architects and verification engineers to define microarchitecture and ensure correctness * Drive timing closure with synthesis and physical design teams * Participate in design reviews and improve RTL coding practices and methodologies Tasks * 3+ years of industry RTL design experience * Solid understanding of computer architecture fundamentals (pipelines, caches, memory hierarchies) * Proficiency in Verilog/SystemVerilog and RTL coding guidelines * Familiarity with timing constraints, physical design considerations, and EDA flows * Hands-on experience with simulation, synthesis, linting, and static timing analysis tools * Strong problem-solving and cross-functional communication skills Key requirements *

aaaaar_ design teams * Participate in design reviews and improve RTL coding practices and methodologies Tasks * 3+ years of industry RTL design experience * Solid understanding of computer architecture fundamentals (pipelines, caches, memory hierarchies) * Proficiency in Verilog/SystemVerilog and RTL coding guidelines * Familiarity with timing constraints, physical design considerations, and EDA flows * Hands-on experience with simulation, synthesis, linting, and static timing analysis tools * Strong problem-solving and cross-functional communication skills Key requirements *