FPGA / ASIC Engineer

Space Exploration Technologies Corp.

Redmond, WA, United States

3 days ago

Role details

Contract type

Permanent contract

Employment type

Full-time (> 32 hours)

Experience level

Experienced

Experience required

3 years minimum

Working hours

Regular working hours

Job source

www.wayup.com

Tech stack

Bash Shell Computer Engineering Electronic Design Automation Perl (Programming Language) Formal Verification Field-Programmable Gate Array (FPGA) Hardware Description Language Python (Programming Language) SystemVerilog Systems Integration Verilog VHSIC Hardware Description Language (VHDL)

+6 more

Vivado Scripting Application Specific Integrated Circuits Fpga Hardware State Machines Backend

Job description

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. FPGA / ASIC DESIGN ENGINEER RESPONSIBILITIES:

As a Design Engineer you’ll help design, implement and verify complex products that use FPGAs and/or ASICs.
Participate in the micro architecture and design partition within the ASIC/FPGA.
Implement design blocks using Verilog / System Verilog.
Participate in all phases of FPGA design Flow (Synthesis, Place & Route, and Timing Closure).
Work with backend teams to address any layout and timing issues for ASICs.
Bring-up and validate ASICs and FPGAs in the lab.

Requirements

Bachelor of Science Degree in computer engineering, electrical engineering or other engineering disciplines.
3+ years of experience working with complex FPGAs and/or ASICs.
3+ years of experience in Verilog / System Verilog and/or VHDL. PREFERRED SKILLS AND EXPERIENCE:
ASIC / FPGA / SoC system integration experience.
Ability to solve complex problems including clock domain crossings and power optimization.
Experience with latest simulation and verification methodologies.
Understanding of Datapath Pipelines, State Machines, Arithmetic Operations.
Exposure to timing closure techniques.
Experience with high reliability design and implementations.
Excellent scripting skills (csh/bash, Perl, Python etc.).
Experience with EDA tools such as HDL simulators (VCS, Questa, IES), HDL Lint tools (Spyglass), FPGA tools (Xilinx Vivado, Altera Quartus II).
Demonstrate the ability to work in a dynamic environment that includes working with changing needs and requirements.
Team-player, can-do attitude, works well in a group environment while still being able to contribute on an individual basis, enjoys being challenged, learn new skills. ITAR REQUIREMENTS:
To conform to U.S. Government space technology export regulations, applicant must be a U.S. citizen, lawful permanent resident of the U.S., protected individual as defined by 8 U.S.C. 1324b(a)(3), or eligible to obtain the required authorizations from the U.S. Department of State. Learn more about ITAR here.