Principal Digital Design Engineer

Astera Labs
San Jose, CA, United States
3 months ago

Role details

Contract type
Permanent contract
Employment type
Full-time (> 32 hours)
Experience level
Expert
Experience required
8 years minimum
Compensation
$185,000.0 - $230,000.0
Working hours
Regular working hours
Job source

Tech stack

C (Programming Language) Microarchitecture Software Debugging Logic Synthesis of Circuits Ethernet Firmware InfiniBand Python (Programming Language) PCI Express Systems Development Life Cycle Network Switches Scripting
+3 more
Front End Software Development Nvme Programming Languages

Job description

We are looking for Principal Digital Design Engineers with experience developing micro-architecture and implementation of the front-end circuit design, including RTL, synthesis, IP integration, and block-level verification for high performance network controllers. The candidate must have good knowledge of communication/interface protocols such as PCI-Express (Gen-3 and above), Ethernet, Infiniband, DDR, NVMe, USB, etc.

Requirements

Do you have experience in Verification (System development task)?, Do you have a Bachelor’s degree in electrical engineering?, * Strong academic and technical background in electrical engineering. A Bachelor’s degree in EE is required, and a Master’s degree is preferred.

  • +8 years’ experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
  • Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision.
  • Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind!
  • Authorized to work in the US and start immediately.

Required Experience:

  • Hands-on, thorough knowledge of high-speed protocols like PCIe, Ethernet, Infiniband, DDR, NVMe, USB, etc.
  • Proven front end design expertise - architecture, RTL, simulations, synthesis, timing closure, GLS, DFT etc.
  • Full chip or block level ownership from architecture to GDS, driving multiple complex designs to production
  • Experience with Synopsys and/or Cadence digital design tools/flows
  • Good knowledge of design for test (DFT), stuck-at and transition scan test insertion
  • Familiarity with UVM based design verification
  • Silicon bring-up and debug expertise
  • Small-geometry CMOS (28nm) design

Preferred Experience:

  • Firmware development with C-language, scripting with Python or other equivalent programming languages.
  • Development/support for PCIe or Ethernet Switch products.

Benefits & conditions

The base salary range is $185,000.00 USD - $230,000.00 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.

About the company

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

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