Distinguished Technologist, ASIC Design Architect

• Define system and chip-level architecture based on product requirements (throughput, latency, features, power, area, cost).

• Translate system/network/software requirements into microarchitecture, block partitioning, interfaces, and verification strategy.

• Architect high-performance datapaths, control planes, memory subsystems, and I/O (SerDes/PCIe/Ethernet/DDR/HBM) to meet PPA targets.

• Mentor and grow engineering teams; promote architecture best practices and cross-discipline communication.

• Balance technical decisions with schedule, risk and business priorities; present tradeoffs and roadmaps to stakeholders.

We are seeking an experienced ASIC Design Architect to own the hardware architecture, microarchitecture, and successful delivery of complex ASICs from concept through tape-out and silicon bring-up. The ideal candidate combines deep system and RTL expertise with both hands-on technical experience and cross-functional leadership. This role will define requirements, partition function into silicon blocks, lead microarchitecture and implementation strategy, and drive tradeoffs for performance, power, area and schedule., * Bachelor’s or master’s degree in electrical engineering, Computer Engineering or related field

• 15+ years of ASIC design experience with progressive ownership of architecture/microarchitecture; proven record of tape-out(s).

• Strong datapath and system architecture skills: packet pipelines or equivalent high-throughput streaming architectures, buffering, arbitration and QoS/scheduling.

• Experience integrating high-speed SerDes/PHY, MAC/PCS, and external memory controllers (DDR/HBM) and familiarity with signal integrity/clocking issues.

• Excellent cross-functional communication skills; ability to drive tradeoffs with product management, firmware, verification, PD and foundry teams.

Nice-to-have

• Prior experience in datacenter switching/routing ASICs

• Patents or publications in ASIC architecture or networking silicon.

Behavioral & leadership expectations

• Able to set vision and translate it into deliverable milestones and measurable success criteria.

• Strong collaborator: leads cross-functional teams, negotiates priorities, and escalates risks early.

• Mentors engineers, conducts architecture and design reviews, and codifies architecture patterns and best practices.

• Results-oriented: delivers under schedule pressure, balances technical excellence with pragmatic tradeoffs.

The expected salary/wage range for this position is provided below. Actual offer may vary from this range based upon geographic location, work experience, education/training, and/or skill level.

• United States of America: Annual Salary USD 183,000 - 365,000 in Massachusetts // 183,000 - 389,500 in California The listed salary range reflects base salary. Variable incentives may also be offered.

Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world. Our culture thrives on finding new and better ways to accelerate what’s next. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good. If you are looking to stretch and grow your career our culture will embrace you. Open up opportunities with HPE.