Lead Hardware Engineer

Role details

Contract type

Permanent contract

Employment type

Full-time (> 32 hours)

Experience level

Expert

Experience required

5 years minimum

Working hours

Regular working hours

Job source

www.disabledperson.com

Tech stack

C++ (Programming Language) Software Debugging Linux Logic Synthesis of Circuits Perl (Programming Language) Emulators Ethernet Field-Programmable Gate Array (FPGA) Joint Test Action (IEEE Standards) Python (Programming Language) PCI Express Quick EMUlator (QEMU)

+2 more

SystemC Universal Asynchronous Receiver/Transmitter

Requirements

Application or Product Engineering background with minimum 5 to 20 years of experience is required in HW Assisted Verification.
Knowledge of FW/SW/Driver with Linux Boot bring up experience is an essential requirement.
Knowledge of PCIe, HBM and JTAG/UART protocols is must..
ENET protocol & testers like Virtual IXIA is plus., * Digital design with systeme verilog RTL coding from Synthesis point of view..
Experience with emulator ZeBu, Palladium & Veloce. FPGA Protyping experience with HAPS, Protium & ProFPGA is plus.
Ability to put together emulation top level wrapper with DUT/System Level, clocks/reset & FPGA partitioning/Place & Route timing closure for successful model build.
Knowledge of Python, C/Perl scripting is a must.
Expertise in HW assisted Verification TestBench environment : UVM, C++/System C is desired.
Experience integrating and bringing up PCIe Gen6 Protocol Transactor Integration with QeMu is required.Kernel boot, Linux Boot sequences knowledge & debug is must.

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Lead Hardware Engineer

Role details

Tech stack

Requirements

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