Design Engineer

Own design and development of a DSP ASIC block from requirements through silicon bring-up. Perform microarchitecture, RTL development, testing, and system integration. Collaborate with quantum physicists, optics, hardware, and software teams. Contribute to and influence FPGA designs to prepare for ASIC implementation. The summary above was generated by AI

At Atom Computing, we build quantum computers using arrays of optically trapped neutral atoms that will empower customers to achieve unprecedented computational breakthroughs. Join a world-class team of scientists, engineers, and business professionals to advance the state-of-the-art in quantum computing.

Atom Computing is seeking a Senior ASIC Designer to design and develop a digital signal processing (DSP) block for our quantum computing systems. You will own the design from requirements definition through silicon bring-up, making key trade-offs across performance, power, area, and system integration constraints.

Reporting to the ASIC Team Lead, you will work closely with cross-functional teams to translate evolving system requirements into production-ready designs. This role requires deep ASIC development expertise, strong systems thinking, and the ability to independently drive complex design work while maintaining alignment with broader system and product goals.

Due to the need for collaboration with Atom’s theory, software, hardware, and optics teams, this role is required to be in the office in Austin, TX or Boulder, CO at least 3 days per week., * Perform hands-on ASIC design including microarchitecture, RTL development, testing, and integration.

• Work closely with Atom Computing’s quantum physicists, optical engineers, hardware and software engineers to understand use cases and deliver hardware that addresses the needs.
• Participate in the design and development of current FPGA designs. Influence the FPGA design and development process to prepare for ASIC design., Design and architect on-chip GPU/CPU clock domains, collaborate with front-end, physical design, timing, verification and SW teams to implement clock RTL, optimize PPA, support ASIC implementation through sign-off and silicon bring-up.

• MS or PhD in Electrical Engineering, or related field.
• 5+ years of post-degree experience as a hardware engineer., * Have gone through a complete ASIC design cycle
• Experience in digital signal processing algorithms
• Proficiency with RTL (SystemVerilog preferred)
• Experience in implementing large digital signal processing blocks in RTL
• Knowledge of Cadence, Synopsys, or Siemens EDA design tools
• Expertise in FPGA, microprocessor, and related digital circuit design and functions

230K-323K Annually Senior level 230K-323K Annually Senior level Aerospace Lead verification planning and execution for complex ASIC/SoC digital subsystems. Develop UVM testbenches, reference models, scoreboards, protocol monitors, and assertions. Drive coverage closure, regression health, and verification signoff. Identify corner cases, collaborate across design, systems, DFT, firmware, and physical design, and support emulation, prototyping, and post-silicon debug., 20 Days Ago In-Office 136K-265K Annually Senior level 136K-265K Annually Senior level Artificial Intelligence * Computer Vision * Hardware * Robotics * Metaverse Drive physical design of high-frequency, low-power CPUs/GPUs/SoCs at block, cluster, or full-chip level with emphasis on netlist quality: equivalence checking/formal verification, CDC and MTBF analysis, logic synthesis, timing convergence, STA, constraint generation/management, and ECO implementation. Use industry-standard EDA tools and scripting to debug and improve flows. Top Skills: Bist)Clock Domain Crossing (Cdc) CheckingDft (ScanEcoFormal VerificationIndustry-Standard Eda ToolsLogic Equivalence CheckingLogic SynthesisMakeMtbf AnalysisNetlistingPerlPythonRtlStatic Timing Analysis (Sta)TclTransition Faults

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