Principal Fabric/Network Architect

We are seeking a Principal Network Architect to own the datacenter scale-out architecture for our T100 platform. A novel accelerator only delivers value if it can be fed at scale, and this role owns the entire path that does the feeding: from the Linux host networking stack, through our electronic integrated circuit (EIC) acting as a PCIe bridge, out to third-party NICs, and back via DMA into HBM. The ideal candidate has built RDMA transports that ran in production, is equally comfortable in kernel networking code and in PCIe protocol details, and can write specifications that both digital design and software teams implement against. This role also owns the longer-term architectural case for a Neurophos DPU., * Own the end-to-end scale-out data path architecture spanning host network stack, EIC PCIe bridge, NIC attachment, and DMA into HBM.

• Define the transport and offload architecture, including RoCEv2 (RDMA over Converged Ethernet v2) and Ultra Ethernet Transport (UET).
• Specify peer-to-peer DMA topology and access control services (ACS) policy across the PCIe hierarchy.
• Define queue and completion semantics exposed to the runtime, in partnership with the software team.
• Drive NIC vendor selection and own the technical engagement with networking silicon partners.
• Model and evaluate collective communication performance for distributed inference workloads.
• Own the architectural case and roadmap for a future Neurophos DPU (data processing unit) and for scale-up fabric in a later phase.
• Represent Neurophos in relevant standards bodies and the data center networking community.
• Establish networking architecture practices and mentor engineers across Architecture and Software.

• BS/MS/PhD in Computer Science, Electrical Engineering, or a related field.
• 10+ years in datacenter networking architecture, including RDMA transports deployed at scale.
• Deep working knowledge of the Linux host networking stack: kernel networking, VFIO, DPDK or libfabric, and IOMMU/IOVA behavior.
• PCIe fluency: root complex versus endpoint roles, bridges, peer-to-peer transactions, ACS, and Gen5/Gen6 signaling and protocol.
• Familiarity with merchant NIC and switch silicon.
• Demonstrated ability to write architecture specifications that digital design and software teams can implement against.
• Excellent communication skills and comfort leading cross-functional technical discussions.

Preferred Skills

• Participation in the Ultra Ethernet Consortium (UEC) or a comparable standards body.
• DPU or SmartNIC architecture experience.
• Congestion control design and evaluation.
• Experience bringing a novel accelerator into a production datacenter network.
• Familiarity with collective communication libraries (NCCL, RCCL, or equivalent) and distributed inference serving.
• Understanding of ML inference workload characteristics and their network demands.
• Experience with hyperscaler qualification and deployment processes.

$250,000 - $300,000 a year - Full-time, Pulled from the full job description

• Health insurance
• 401(k) matching
• Vision insurance
• Health savings account
• Dental insurance
• Stock options
• Unlimited paid time off, Join a team that invests in your future and your well-being. At Neurophos, we offer:
• 100% coverage of base health plan premiums for you and your dependents, plus HSA contributions.
• Unlimited PTO. No rigid vacation banks, just a focus on delivery.
• 401(k) matching and stock option opportunities to ensure our success is your success.
• Full suite of voluntary benefits, including Dental, Vision, Life, Hospital, Critical Illness, and Accident insurance.
• Personalized Benefits. Choose the plans that fit your life and take the cash back for those that don’t.

Compensation Range: $250K - $300K

The demand for new data centers and AI compute is rapidly outpacing the planet’s energy capacity. Digital solutions are hitting a power wall as we approach the physical limits of traditional silicon. Conquering this bottleneck means rethinking the fundamental architecture of inference compute. The industry’s current path can’t meet the need, so we’re taking a different approach.

Instead of traditional electronic circuits, we use silicon photonics and an active, programmable metasurface to perform matrix multiplications at the speed of light. Our optical cells are 10,000x smaller than traditional photonic components, enabling unprecedented density. By using photonics instead of electricity, our chips become more efficient as they scale. This architecture will deliver up to 100 times the energy efficiency of existing solutions while significantly improving performance for large-scale AI inference.

We’ve assembled a world-class team of industry veterans and recently raised a $110M Series A led by Gates Frontier. Participants include M12 (Microsoft’s Venture Fund), Carbon Direct Capital, Aramco Ventures, Bosch Ventures, Tectonic Ventures, Space Capital, and others.

Join us and shape the future of computing!