Digital ASIC Design Engineer

IC Resources

Barcelona, Spain

5 days ago

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Role details

Contract type

Permanent contract

Employment type

Full-time (> 32 hours)

Compensation

€90,000.0 - €130,000.0

Working hours

Regular working hours

Job source

www.jobleads.com

Tech stack

Field-Programmable Gate Array (FPGA) SystemVerilog Application Specific Integrated Circuits

Requirements

The role requires strong experience in ASIC/FPGA design, UVM environments, and SystemVerilog for IP/SOC designs. Visa sponsorship and relocation support are offered if needed.

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Good distractions

Talks and stories from around this role — technically off-topic, practically not.

Moments

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Exploring internal AI product initiatives and global engineering roles

Maria Apazoglou · Coffee With Developers

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Building full-stack superconducting quantum hardware

Alexander Glätzle +3 · World Congress 2024

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Designing versatile software interfaces using the onion principle

Bjarne Stroustrup · World Congress 2022

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Addressing the competitive landscape of specialized hardware demands

Hazal Mestci +1 · Coffee With Developers

Videos

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Your next 10x engineer isn't in your city. Refactor accordingly. thumbnail